74ALVC374PW,118 Nexperia

74ALVC374 Octal D-type ip-op positive-edge trigger 3-state Rev. 02 17 October 2007 Product data sheet 1. General description The 74ALVC374 is an octal D-type ip-op featuring separate D-type inputs for each ip-op and 3-state outputs for bus-oriented applications. A clock input (CP) and an outputs enable input (OE) are common to all ip-ops. The eight ip-ops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW to HIGH CP transition. When pin OE is LOW, the contents of the eight ip-ops is available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the ip-ops. The 74ALVC374 is functionally identical to the 74ALVC574, but has a different pin arrangement. 2. Features Wide supply voltage range from 1.65 V to 3.6 V 3.6 V tolerant inputs/outputs CMOS low power consumption Direct interface with TTL levels (2.7 V to 3.6 V) Power-down mode Latch-up performance exceeds 250 mA Complies with JEDEC standards: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A 115-A exceeds 200 V74ALVC374 NXP Semiconductors Octal D-type ip-op positive-edge trigger 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ALVC374D - 40 Cto+85 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74ALVC374PW - 40 Cto+85 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 74ALVC374BQ - 40 Cto+85 C DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1 thin quad at package no leads 20 terminals body 2.5 4.5 0.85 mm 4. Functional diagram 1 EN 11 C1 11 3 2 1D CP 3 2 D0 Q0 4 5 4 5 D1 Q1 7 6 7 6 D2 Q2 8 9 8 9 D3 Q3 13 12 13 12 D4 Q4 14 15 14 15 D5 Q5 17 16 D6 Q6 17 16 18 19 D7 Q7 18 19 OE 1 mna891 mna196 Fig 1. Logic symbol Fig 2. IEC logic symbol 74ALVC374 2 NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 17 October 2007 2 of 17