74ALVC573BQ,115 NXP

74ALVC573 Octal D-type transparent latch; 3-state Rev. 03 26 October 2007 Product data sheet 1. General description The 74ALVC573 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable (LE) input and an outputs enable (OE) input are common to all latches. When pin LE is HIGH, data at the D-inputs (pins D0 to D7) enters the latches. In this condition, the latches are transparent, that is, a latch output will change each time its corresponding D-input changes. When pin LE is LOW, the latches store the information that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of pin LE. When pin OE is LOW, the contents of the eight latches are available at the Q-outputs (pins Q0 to Q7). When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of input pin OE does not affect the state of the latches. The 74ALVC573 is functionally identical to the 74ALVC373, but has a different pin arrangement. 2. Features Wide supply voltage range from 1.65 V to 3.6 V 3.6 V tolerant inputs/outputs CMOS low power consumption Direct interface with TTL levels (2.7 V to 3.6 V) Power-down mode Latch-up performance exceeds 250 mA Complies with JEDEC standards: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A 115-A exceeds 200 V74ALVC573 Nexperia Octal D-type transparent latch; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ALVC573D -40 Cto+85 C SO20 plastic small outline package; 20 leads; SOT163-1 body width 7.5 mm 74ALVC573PW -40 Cto+85 C TSSOP20 plastic thin shrink small outline package; 20 leads; SOT360-1 body width 4.4 mm 74ALVC573BQ 40- Cto+85 C DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1 thin quad at package; no leads; 20 terminals; body 2.5 4.5 0.85 mm 4. Functional diagram 11 C1 1 EN1 1 2 19 1D OE 2 19 D0 Q0 3 18 3 18 D1 Q1 4 17 4 17 D2 Q2 5 16 5 16 D3 Q3 6 15 6 15 D4 Q4 7 14 7 14 D5 Q5 8 13 D6 Q6 8 13 9 12 D7 Q7 9 12 LE 11 mna807 mna808 Fig 1. Logic symbol Fig 2. IEC logic symbol 2 19 D0 Q0 3 D1 Q1 18 4 D2 Q2 17 5 D3 16 Q3 LATCH 3-STATE 6 15 D4 1 to 8 OUTPUTS Q4 7 D5 Q5 14 8 D6 Q6 13 9 12 D7 Q7 11 LE OE 1 mna809 Fig 3. Functional diagram 74ALVC573_3 Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 03 26 October 2007 2 of 17