74ACTQ16374SSC ON Semiconductor

74ACTQ16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs June 1991 Revised May 2005 74ACTQ16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs General Description Features The ACTQ16374 contains sixteen non-inverting D-type flip- Utilizes Fairchild FACT Quiet Series technology flops with 3-STATE outputs and is intended for bus oriented Guaranteed simultaneous switching noise level and applications. The device is byte controlled. A buffered clock dynamic threshold performance (CP) and Output Enable (OE) are common to each byte Guaranteed pin-to-pin output skew and can be shorted together for full 16-bit operation. Buffered Positive edge-triggered clock The ACTQ16245 utilizes Fairchild Quiet Series technol- ogy to guarantee quiet output switching and improved Separate control logic for each byte dynamic threshold performance. FACT Quiet Series fea- 16-bit version of the ACTQ374 tures GTO output control for superior performance. Outputs source/sink 24 mA Additional specs for Multiple Output Switching Output loadings specs for both 50 pF and 250 pF loads Ordering Code: Order Number Package Number Package Description 74ACTQ16374SSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide 74ACTQ16374MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering code. Connection Diagram Logic Symbol Pin Descriptions Pin Description Names OE Output Enable Input (Active LOW) n CP Clock Pulse Input n I I Inputs 0 15 O O Outputs 0 15 FACT, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation. 2005 Fairchild Semiconductor Corporation DS010935 www.fairchildsemi.comFunctional Description Truth Tables The ACTQ16374 consists of sixteen edge-triggered flip- Inputs Outputs flops with individual D-type inputs and 3-STATE true out- puts. The device is byte controlled with each byte function- CP OE I I O O 1 1 0 7 0 7 ing identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. LH H Each byte has a buffered clock and buffered Output Enable LL L common to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store L L X (Previous) the state of their individual D inputs that meet the setup and XHX Z hold time requirements on the LOW-to-HIGH Clock (CP ) n transition. With the Output Enable (OE ) LOW, the con- n Inputs Outputs tents of the flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. n CP OE I I O O 2 2 8 15 8 15 Operation of the OE input does not affect the state of the n LH H flip-flops. LL L L L X (Previous) XHX Z H HIGH Voltage Level L LOW Voltage Level X Immaterial Z HIGH Impedance LOW-to-HIGH Transition Logic Diagrams Byte 1 (0:7) Byte 2 (8:15) www.fairchildsemi.com 2 74ACTQ16374