74ACQ646 74ACTQ646 Quiet Series Octal Transceiver/Register with 3-STATE Outputs January 1990 Revised September 2000 74ACQ646 74ACTQ646 Quiet Series Octal Transceiver/Register with 3-STATE Outputs General Description Features The ACQ/ACTQ646 consist of registered bus transceiver Guaranteed simultaneous switching noise level and circuits, with outputs, D-type flip-flops, and control circuitry dynamic threshold performance providing multiplexed transmission of data directly from the Guaranteed pin-to-pin skew AC performance input bus or from the internal storage registers. Data on the Independent registers for A and B busses A or B bus will be loaded into the respective registers on Multiplexed real-time and stored data transfers the LOW-to-HIGH transition of the appropriate clock pin (CPAB or CPBA). The four fundamental handling functions 300 mil slim dual-in-line package available are illustrated in Figure 1, Figure 2, Figure 3 and Outputs source/sink 24 mA Figure 4. Faster prop delays than the standard AC/ACT646 The ACQ/ACTQ utilizes Fairchild Quiet Series technol- ogy to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series fea- tures GTO output control and undershoot corrector in addition to a split ground bus for superior performance. Ordering Code: Order Number Package Number Package Description 74ACQ646SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ACQ646ASPC N24 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74ACTQ646SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ACTQ646ASPC N24 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering code. Connection Diagram Pin Descriptions Pin Names Descriptions A A Data Register A Inputs 0 7 Data Register A Outputs B B Data Register B Inputs 0 7 Data Register B Outputs CPAB, CPBA Clock Pulse Inputs SAB, SBA Transmit/Receive Inputs G Output Enable Input DIR Direction Control Input FACT, Quiet Series, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation 2000 Fairchild Semiconductor Corporation DS010635 www.fairchildsemi.comLogic Symbols IEEE/IEC Function Table Inputs Data I/O (Note 1) Function G DIR CPAB CPBA SAB SBA A A B B 0 7 0 7 H X H or L H or L X X Isolation HX X X X Input Input Clock A Data into A Register n HX X X X Clock B Data into B Register n LH X X L X A to B Real Time (Transparent Mode) n n LH X L X Input Output Clock A Data into A Register n L H H or L X H X A Register to B (Stored Mode) n LH X H X Clock A Data into A Register and Output to B n n LL X X X L B to A Real Time (Transparent Mode) n n LL X X L Output Input Clock B Data into B Register n L L X H or L X H B Register to A (Stored Mode) n LL X X H Clock B Data into B Register and Output to A n n H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. www.fairchildsemi.com 2 74ACQ646 74ACTQ646