74ACTQ273 Quiet Series Octal D-Type Flip-Flop May 2007 74ACTQ273 tm Quiet Series Octal D-Type Flip-Flop Features General Description I reduced by 50% The ACTQ273 has eight edge-triggered D-type flip-flops CC with individual D inputs and Q outputs. The common Guaranteed simultaneous switching noise level and buffered Clock (CP) and Master Reset (MR) input load dynamic threshold performance and reset (clear) all flip-flops simultaneously. Guaranteed pin-to-pin skew AC performance The register is fully edge-triggered. The state of each Improved latch-up immunity D-type input, one setup time before the LOW-to-HIGH Buffered common clock and asynchronous master clock transition, is transferred to the corresponding flip- reset flop s Q output. Outputs source/sink 24mA All outputs will be forced LOW independently of Clock or 4kV minimum ESD immunity Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. The ACTQ utilizes Fairchild Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addi- tion to a split ground bus for superior performance. Ordering Information Package Order Number Number Package Description 74ACTQ273SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ACTQ273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACTQ273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number. Connection Diagram Pin Description Pin Names Description D D Data Inputs 0 7 Master Reset MR CP Clock Pulse Input Q Q Data Outputs 0 7 FACT, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation. 1989 Fairchild Semiconductor Corporation www.fairchildsemi.com 74ACTQ273 Rev. 1.474ACTQ273 Quiet Series Octal D-Type Flip-Flop Logic Symbols Mode Select-Function Table Inputs Outputs Operating Mode MR CP D Q n n Reset (Clear) L X X L Load 1 H H H Load 0 H L L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial IEEE/IEC = LOW-to-HIGH Transition Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 1989 Fairchild Semiconductor Corporation www.fairchildsemi.com 74ACTQ273 Rev. 1.4 2