74ACQ573, 74ACTQ573 Quiet Series Octal Latch with 3-STATE Outputs April 2007 74ACQ573, 74ACTQ573 tm Quiet Series Octal Latch with 3-STATE Outputs Features General Description I and I reduced by 50% The ACQ/ACTQ573 is a high-speed octal latch with buff- CC OZ ered common Latch Enable (LE) and buffered common Guaranteed simultaneous switching noise level and Output Enable (OE) inputs. The ACQ/ACTQ573 is func- dynamic threshold performance tionally identical to the ACQ/ACTQ373 but with inputs Guaranteed pin-to-pin skew AC performance and outputs on opposite sides of the package. The ACQ/ Improved latch-up immunity ACTQ utilizes Fairchild s Quiet Series technology to Inputs and outputs on opposite sides of package allow guarantee quiet output switching and improved dynamic easy interface with microprocessors threshold performance. FACT Quiet Series features Outputs source/sink 24mA GTO output control and undershoot corrector in addi- tion to a split ground bus for superior performance. Ordering Information Package Order Number Number Package Description 74ACQ573SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ACQ573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACQ573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACTQ573SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ACTQ573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACTQ573QSC MQA20 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide 74ACTQ573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number. Connection Diagram Pin Descriptions Pin Names Description D D Data Inputs 0 7 LE Latch Enable Input 3-STATE Output Enable Input OE O O 3-STATE Latch Outputs 0 7 FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation. 1990 Fairchild Semiconductor Corporation www.fairchildsemi.com 74ACQ573, 74ACTQ573 Rev. 1.574ACQ573, 74ACTQ573 Quiet Series Octal Latch with 3-STATE Outputs Logic Symbol Functional Description The ACQ/ACTQ573 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the D inputs enters the latches. n In this condition the latches are transparent, i.e., a latch output will change state each time its D-type input changes. When LE is LOW the latches store the informa- tion that was present on the D-type inputs at setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. IEEE/IEC When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. Truth Table Inputs Outputs OE LE D O n LH H H LH L L LL X O 0 HX X Z H = HIGH Voltage L = LOW Voltage Z = High Impedance X = Immaterial = Previous O before HIGH-to-LOW transition of O 0 0 Latch Enable Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 1990 Fairchild Semiconductor Corporation www.fairchildsemi.com 74ACQ573, 74ACTQ573 Rev. 1.5 2