74AVC16373DGG,118 Nexperia

74AVC16373 16-bit D-type transparent latch 3.6 V tolerant 3-state Rev. 3 20 February 2018 Product data sheet 1 General description The 74AVC16373 is a 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. One latch enable (LE) input and one output enable (OE) input are provided per 8-bit section. The 74AVC16373 consist of two sections of eight D-type transparent latches with 3-state true outputs. The 74AVC16373 is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-impedance output state during power-up or power-down, pin nOE should be tied to V through a pull-up resistor (Live Insertion). CC A dynamic controlled output (DCO) circuitry is implemented to support termination line drive during transient (see Figure 5). 2 Features and benefits Wide supply voltage range from 1.2 V to 3.6 V Complies with JEDEC standards: JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-1A (2.7 V to 3.6 V) CMOS low power consumption Input/output tolerant up to 3.6 V Dynamic Controlled Output (DCO) circuit dynamically changes output impedance, resulting in noise reduction without speed degradation Low inductance multiple V and GND pins to minimize noise and ground bounce CC Supports Live Insertion 3 Ordering information Table 1.Ordering information Type number Package Temperature range Name Description Version 74AVC16373DGG 40 C to +85 C TSSOP48 plastic thin shrink small outline package SOT362-1 48 leads body width 6.1 mmNexperia 74AVC16373 16-bit D-type transparent latch 3.6 V tolerant 3-state 4 Functional diagram 1 1EN 1OE 48 1LE C3 1 24 24 2EN 2OE 25 C4 2LE 1OE 2OE 47 1D0 1Q0 2 47 2 1D0 1 1Q0 3D 46 1D1 1Q1 3 46 3 1D1 1Q1 44 1D2 1Q2 5 44 5 1D2 1Q2 43 1D3 1Q3 6 6 43 41 1D4 1Q4 8 1D3 1Q3 8 41 40 1D5 1Q5 9 1D4 1Q4 40 9 38 1D6 1Q6 11 1D5 1Q5 38 11 37 1D7 1Q7 12 1D6 1Q6 36 2D0 2Q0 13 37 12 1D7 1Q7 35 2D1 2Q1 14 36 13 2D0 4D 2 2Q0 33 2D2 2Q2 16 14 35 2D1 2Q1 32 2D3 2Q3 17 33 16 2D2 2Q2 30 2D4 2Q4 19 32 17 2D3 2Q3 29 2D5 2Q5 20 30 19 2D4 2Q4 27 2D6 2Q6 22 29 20 2D5 26 2D7 2Q7 23 2Q5 27 22 2D6 2Q6 1LE 2LE 26 23 2D7 2Q7 48 25 001aam007 mgu770 Figure 1.Logic symbol Figure 2.IEC logic symbol 1D0 D Q 1Q0 2D0 D Q 2Q0 LATCH LATCH 1 9 LE LE LE LE 1LE 2LE 1OE 2OE to 7 other channels to 7 other channels mgu769 Figure 3.Logic diagram 74AVC16373 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved. Product data sheet Rev. 3 20 February 2018 2 / 15