74AVC16374DGG,118 NXP

74AVC16374 16-bit edge triggered D-type flip-flop 3.6 V tolerant 3-state Rev. 3 16 August 2013 Product data sheet 1. General description The 74AVC16374 is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. The 74AVC16374 consist of 2 sections of 8 edge-triggered flip-flops. A clock input (CP) and an output enable (OE) are provided per 8-bit section. The 74AVC16374 is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-impedance output state during power-up or power-down, nOE should be tied to VCC through a pull-up resistor (Live Insertion). A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line drive during transient (see Figure 5 and Figure 6). 2. Features and benefits Wide supply voltage range from 1.2 V to 3.6 V Complies with JEDEC standards: JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-1A (2.7 V to 3.6 V) CMOS low power consumption Input/output tolerant up to 3.6 V Dynamic Controlled Output (DCO) circuit dynamically changes output impedance, resulting in noise reduction without speed degradation Low inductance multiple V and GND pins to minimize noise and ground bounce CC Supports Live Insertion 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AVC16374DGG 40 C to +85 C TSSOP48 plastic thin shrink small outline package SOT362-1 48 leads body width 6.1 mm74AVC16374 Nexperia 16-bit edge triggered D-type flip-flop 3.6 V tolerant 3-state 4. Functional diagram 1 1EN 1OE 1 24 48 1CP C1 24 1OE 2OE 2OE 2EN 25 47 1D0 1Q0 2 2CP C2 46 1D1 1Q1 3 2 47 1D0 1D 1 1Q0 44 1D2 1Q2 5 46 3 1D1 1Q1 43 1D3 1Q3 6 44 5 1D2 1Q2 41 1D4 1Q4 8 6 43 1D3 1Q3 40 1D5 1Q5 9 8 41 1D4 1Q4 38 1D6 1Q6 11 40 9 1D5 1Q5 1D7 1Q7 12 37 38 11 1D6 1Q6 36 2D0 2Q0 13 12 37 1D7 1Q7 35 2D1 2Q1 14 36 13 2D0 2Q0 2D 2 2D2 2Q2 16 33 35 14 2D1 2Q1 32 2D3 2Q3 17 33 16 2D2 2Q2 30 2D4 2Q4 19 32 17 2D3 2Q3 2D5 2Q5 20 29 30 19 2D4 2Q4 27 2D6 2Q6 22 29 20 2D5 2Q5 26 2D7 2Q7 23 27 22 2D6 2Q6 1CP 2CP 26 23 2D7 2Q7 48 25 mna576 mna577 Fig 1. IEC logic symbol Fig 2. Logic symbol 1D0 1Q0 D Q CP FF1 1CP 1OE to 7 other channels 2D0 D Q 2Q0 CP FF9 2CP 2OE to 7 other channels mna578 Fig 3. Logic diagram 74AVC16374 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 3 16 August 2013 2 of 16