74F74 Dual D-Type Positive Edge-Triggered Flip-Flop April 1988 Revised September 2000 74F74 Dual D-Type Positive Edge-Triggered Flip-Flop the outputs until the next rising edge of the Clock Pulse General Description input. The F74 is a dual D-type flip-flop with Direct Clear and Set Asynchronous Inputs: inputs and complementary (Q, Q) outputs. Information at LOW input to S sets Q to HIGH level the input is transferred to the outputs on the positive edge D of the clock pulse. Clock triggering occurs at a voltage level LOW input to C sets Q to LOW level D of the clock pulse and is not directly related to the transition Clear and Set are independent of clock time of the positive-going pulse. After the Clock Pulse input Simultaneous LOW on C and S threshold voltage has been passed, the Data input is D D locked out and information present will not be transferred to makes both Q and Q HIGH Ordering Code: Order Number Package Number Package Description 74F74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74F74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F74PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009469 www.fairchildsemi.comUnit Loading/Fan Out U.L. Input I /I IH IL Pin Names Description HIGH/LOW Output I /I OH OL D , D Data Inputs 1.0/1.0 20 A/0.6 mA 1 2 CP , CP Clock Pulse Inputs (Active Rising Edge) 1.0/1.0 20 A/0.6 mA 1 2 C , C Direct Clear Inputs (Active LOW) 1.0/3.0 20 A/1.8 mA D1 D2 S , S Direct Set Inputs (Active LOW) 1.0/3.0 20 A/1.8 mA D1 D2 Q , Q , Q , Q Outputs 50/33.3 1 mA/20 mA 1 1 2 2 Truth Table Inputs Outputs S C CP D Q Q D D LH X X H L HL X X L H LL X X H H HH hH L HH lL H HH L X Q Q 0 0 H (h) = HIGH Voltage Level L (l) = LOW Voltage Level X = Immaterial Q = Previous Q (Q) before LOW-to-HIGH Clock Transition 0 Lower case letters indicate the state of the referenced input or output one setup time prior to the LOW-to-HIGH clock transition. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74F74