74AC174 74ACT174 Hex D-Type Flip-Flop with Master Reset November 1988 Revised October 2000 74AC174 74ACT174 Hex D-Type Flip-Flop with Master Reset General Description Features The AC/ACT174 is a high-speed hex D-type flip-flop. The I reduced by 50% CC device is used primarily as a 6-bit edge-triggered storage Outputs source/sink 24 mA register. The information on the D inputs is transferred to ACT174 has TTL-compatible inputs storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear all flip- flops. Ordering Code: Order Number Package Number Package Description 74AC174SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74AC174SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC174MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC174PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74ACT174SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74ACT174SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT174MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT174PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description D D Data Inputs 0 5 CP Clock Pulse Input MR Master Reset Input Q Q Outputs 0 5 FACT is a trademark of Fairchild Semiconductor Corporation. 2000 Fairchild Semiconductor Corporation DS009935 www.fairchildsemi.comFunctional Description Truth Table The AC/ACT174 consists of six edge-triggered D-type flip- Inputs Output flops with individual D inputs and Q outputs. The Clock (CP) and Master Reset (MR) are common to all flip-flops. MR CP D Q Each D inputs state is transferred to the corresponding flip- flops output following the LOW-to-HIGH Clock (CP) transi- LX X L tion. A LOW input to the Master Reset (MR) will force all H HH outputs LOW independent of Clock or Data inputs. The AC/ ACT174 is useful for applications where the true output H LL only is required and the Clock and Master Reset are com- HL X Q mon to all storage elements. H = HIGH Voltage Level L = LOW Voltage Level = LOW-to-HIGH Transition X = Immaterial Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74AC174 74ACT174