74AC175, 74ACT175 Quad D-Type Flip-Flop
April 2007
74AC175, 74ACT175
tm
Quad D-Type Flip-Flop
Features General Description
I reduced by 50% The AC/ACT175 is a high-speed quad D-type flip-flop.
CC
The device is useful for general flip-flop requirements
Edge-triggered D-type inputs
where clock and clear inputs are common. The informa-
Buffered positive edge-triggered clock
tion on the D-type inputs is stored during the LOW-to-
Asynchronous common reset
HIGH clock transition. Both true and complemented out-
True and complement output
puts of each flip-flop are provided. A Master Reset input
Outputs source/sink 24mA resets all flip-flops, independent of the Clock or D-type
inputs, when LOW.
ACT175 has TTL-compatible inputs
Ordering Information
Order Package
Number Number Package Description
74AC175SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Body
74AC175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC175MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC175PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74ACT175SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Body
74ACT175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT175MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number.
Connection Diagram Pin Descriptions
Pin Names Description
D D Data Inputs
0 3
CP Clock Pulse Input
Master Reset Input
MR
Q True Outputs
Q
0 3
Q Q Complement Outputs
0 3
FACT is a trademark of Fairchild Semiconductor Corporation.
1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC175, 74ACT175 Rev. 1.474AC175, 74ACT175 Quad D-Type Flip-Flop
Logic Symbol Functional Description
The AC/ACT175 consists of four edge-triggered D-type
outputs.
flip-flops with individual D inputs and Q and Q
The Clock and Master Reset are common. The four flip-
flops will store the state of their individual D inputs on the
LOW-to-HIGH clock (CP) transition, causing individual Q
and Q outputs to follow. A LOW input on the Master
Reset (MR) will force all Q outputs LOW and Q outputs
HIGH independent of Clock or Data inputs. The AC/
ACT175 is useful for general logic applications where a
common Master Reset and Clock are acceptable.
Truth Table
IEEE/IEC
Inputs @ t , MR = H Outputs @ t
n n+1
D Q Q
n n n
LL H
HH L
H = HIGH Voltage Level
L = LOW Voltage Level
t = Bit Time before Clock Pulse
n
= Bit Time after Clock Pulse
t
n+1
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
Figure 1.
1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC175, 74ACT175 Rev. 1.4 2