74ALVC541D-Q100J Nexperia

74ALVC541-Q100 Octal buffer/line driver 3-state Rev. 3 30 April 2021 Product data sheet 1. General description The 74ALVC541-Q100 is an octal non-inverting buffer/line drivers with 3-state bus compatible outputs. The 3-state outputs are controlled by the output enable inputs OE0 and OE1. A HIGH on OEn causes the outputs to assume a high-impedance OFF-state. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 3) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 3) Specified from -40 C to +85 C Wide supply voltage range from 1.65 V to 3.6 V Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V ) JESD8-5 (2.3 V to 2.5 V) JESD8B (2.7 V to 3.6 V) 3.6 V tolerant inputs/outputs CMOS LOW power consumption Direct interface with TTL levels (2.7 V to 3.6 V) Power-down mode Latch-up performance exceeds 250 mA ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ALVC541D-Q100 -40 C to +85 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74ALVC541PW-Q100 -40 C to +85 C TSSOP20 plastic thin shrink small outline package SOT360-1 20 leads body width 4.4 mm 74ALVC541BQ-Q100 -40 C to +85 C DHVQFN20 plastic dual in-line compatible thermal SOT764-1 enhanced very thin quad flat package no leads 20 terminals body 2.5 4.5 0.85 mmNexperia 74ALVC541-Q100 Octal buffer/line driver 3-state 4. Functional diagram Y0 A0 2 18 A1 Y1 3 17 A2 Y2 4 16 A3 Y3 5 15 A4 Y4 6 14 1 & EN 19 A5 Y5 7 13 2 18 17 3 A6 Y6 8 12 4 16 5 15 Y7 A7 11 9 6 14 13 7 12 8 OE0 1 9 11 OE1 19 mna179 mna180 Fig. 1. Logic symbol Fig. 2. IEC logic symbol 5. Pinning information 5.1. Pinning 74ALVC541 terminal 1 index area A0 2 19 OE1 3 18 A1 Y0 A2 4 17 Y1 74ALVC541 A3 5 16 Y2 OE0 1 20 V A4 6 15 Y3 CC A0 2 19 OE1 A5 7 14 Y4 A1 3 18 Y0 (1) 8 13 A6 GND Y5 A2 4 17 Y1 A7 9 12 Y6 A3 5 16 Y2 A4 6 15 Y3 001aah061 A5 7 14 Y4 A6 8 13 Y5 Transparent top view A7 9 12 Y6 (1) This is not a ground pin. There is no electrical or GND 10 11 Y7 mechanical requirement to solder the pad. In case 001aah060 soldered, the solder land should remain floating or connected to GND. Fig. 3. Pin configuration SOT163-1 (SO20) and SOT360-1 (TSSOP20) Fig. 4. Pin configuration SOT764-1 (DHVQFN20) 74ALVC541 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 3 30 April 2021 2 / 13 10 1 GND OE0 Y7 11 20 V CC