74ALVCH16823 18-bit bus-interface D-type flip-flop with reset and enable 3-state Rev. 3 1 February 2018 Product data sheet 1 General description The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. Incorporates bushold data inputs which eliminate the need for external pull-up resistors to hold unused inputs. The 74ALVCH16823 consists of two sections of nine edge-triggered flip-flops. A clock (nCP) input, an output-enable (nOE) input, a master reset (nMR) input and a clock- enable (nCE) input are provided for each total 9-bit section. With the clock-enable (nCE) input LOW, the D-type flip-flops will store the state of their individual nDn-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH nCP transition. Taking nCE HIGH disables the clock buffer, thus latching the outputs. Taking the master reset (nMR) input LOW causes all the nQn outputs to go LOW independently of the clock. When nOE is LOW, the contents of the flip-flops are available at the outputs. When the nOE is HIGH, the outputs go to the high impedance OFF-state. Operation of the nOE input does not affect the state of flip-flops. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. 2 Features and benefits Wide supply voltage range from 1.2 V to 3.6 V CMOS low-power consumption Direct interface with TTL levels Current drive 24 mA at 3.0 V MULTIBYTE flow-through standard pin-out architecture Low inductance multiple V and GND pins for minimum noise and ground bounce CC Output drive capability 50 transmission lines at 85C All data inputs have bushold Complies with JEDEC standard no. 8-1A Complies with JEDEC standards: JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V CDM JESD22-C101E exceeds 1000 VNexperia 74ALVCH16823 18-bit bus-interface D-type flip-flop with reset and enable 3-state 3 Ordering information Table 1.Ordering information Type number Package Temperature range Name Description Version 74ALVCH16823DGG 40 C to +85 C TSSOP56 plastic thin shrink small outline package 56 leads SOT364-1 body width 6.1 mm 4 Functional diagram 2 1OE EN1 1 1MR R2 2MR 1OE 55 28 2 1CE G3 1MR 2OE 56 1 27 1CP 3C4 27 2OE EN5 28 2MR R6 1D0 1Q0 30 54 3 2CE G7 29 1D1 1Q1 7C8 2CP 52 5 1D2 1Q2 51 6 54 3 1D3 1Q3 1D0 4D 1,2 1Q0 49 8 52 5 1D4 1Q4 1D1 1Q1 48 9 51 6 1D5 1Q5 1D2 1Q2 47 10 49 8 1D6 1Q6 1D3 1Q3 45 12 48 9 1D7 1Q7 1D4 1Q4 44 13 47 10 1D8 1Q8 1D5 1Q5 43 14 45 12 2D0 2Q0 1D6 1Q6 42 15 44 13 2D1 2Q1 1D7 1Q7 41 16 43 14 2D2 2Q2 1D8 1Q8 40 17 42 15 2D3 2Q3 2D0 8D 5,6 2Q0 38 19 41 16 2D4 2Q4 2D1 2Q1 37 20 40 17 2D5 2Q5 2D2 2Q2 36 21 38 19 2D6 2Q6 2D3 2Q3 34 23 37 20 2D7 2Q7 2D4 2Q4 33 24 36 21 2D8 2Q8 2D5 2Q5 31 26 34 23 2D6 2Q6 33 24 2CE 1CP 2D7 2Q7 56 30 31 26 2CP 1CE 2D8 2Q8 29 55 aaa-028141 001aad242 Figure 1.Logic symbol Figure 2.IEC logic symbol V CC data input to internal circuit 001aad245 Figure 3.Bushold circuit (one data input) 74ALVCH16823 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved. Product data sheet Rev. 3 1 February 2018 2 / 18