STE100P 10/100 FAST ETHERNET 3.3V TRANSCEIVER 1 DESCRIPTION Figure 1. Package The STE100P, also referred to as STEPHY1, is a high performance Fast Ethernet physical layer in- terface for 10Base-T and 100Base-TX applica- tions. TQFP64 (10x10x1.40mm) It was designed with advanced CMOS technology to provide a Media Independent Interface (MII) for easy attachment to 10/100 Media Access Control- Table 1. Order Codes lers (MAC) and a physical media interface for Part Number Package 100Base-TX of IEEE802.3u and 10Base-T of IEEE802.3. STE100P TQFP64 The STEPHY1 supports both half-duplex and full- (*) TQFP64 E-STE100P duplex operation, at 10 and 100 Mbps operation. (*) ECOPACK (see Section 9) Its operating mode can be set using auto-negotia- tion, parallel detection or manual control. It also al- lows for the support of auto-negotiation functions Support for IEEE802.3x flow control for speed and duplex detection. IEEE802.3u Auto-Negotiation support for 10Base-T and 100Base-TX 2FEATURES MII interface Standard CSMA/CD or full duplex operation 2.1 Industry standard supported IEEE802.3u 100Base-TX and IEEE802.3 Industrial temperature compliant 10Base-T compliant Figure 2. Block Diagram LEDS LEDS TX Channel 100Mb/s Parallel to TX CLK 4B/5B Scrambler NRZ To NRZI Binary To MLT3 Serial Encoder Encoder TXD 3:0 TRANSMITTER TXP TX ER 10/100 TXN TX EN 10Mb/s Link Pulse NRZ To Manchester 10 TX Generator Encoder Filter MDC MDIO Auto System Loopback Clock Negotiation REGISTERS Clock Generation RXD 3:0 RX Channel RX ER Adaptive Binary To MLT3 100Mb/s Equalization RX DV Decoder Descrambler Serial to NRZI To NRZ BaseLine 4B/5B Code Align RX CLK Clock Recovery Wander Parallel Decoder RXP RECEIVER 10/100 RXN 10 TX Filter SMART NRZ To Manchester Link Pulse 10Mb/s HW Squelch Encoder Detector Clock Recovery configuration pins HW Config Power Down Rev. 19 February 2006 1/31 Serial Management MII Interface / ControllerSTE100P 2.2 Physical Layer Integrates the whole Physical layer functions of 100Base-TX and 10Base-T Provides Full-duplex operation on both 100Mbps and 10Mbps modes Provides Auto-negotiation(NWAY) function of full/half duplex operation for both 10 and 100 Mbps Provides MLT-3 transceiver with DC restoration for Base-line wander compensation Provides transmit wave-shaper, receive filters, and adaptive equalizer Provides loop-back modes for diagnostic Builds in Stream Cipher Scrambler/ De-scrambler and 4B/5B encoder/decoder Supports external transmit transformer with turn ratio 1:1 Supports external receive transformer with turn ratio 1:1 2.3 LED Display The LED display, consists of five LEDs having the following characteristics: 10 Mbps Speed LED: 10Mbps(on) or 100Mbps(off) 100 Mbps Speed LED: 100Mbps(on) or 10Mbps(off) TX/RX Activity LED: Blinks at 10Hz when receiving, but not colliding Link LED: On when a good link is detected, blinks when there is TX or RX activity Full Duplex / Collision LED: On during Full Duplex operation. Blinks at 20Hz to indicate a collision 2.4 Miscellaneous Standard 64-pin QFP package pinout Figure 3. System Diagram of the STE100P Application Serial LEDs EEPROM MAC STE100P RJ-45 STEPHY1 Device 25 MHz Boot ROM Crystal 2/31 PCI Interface Transformer