Integrated Device Technology, Inc. Document Type: Data Sheet ICS1893BF Document Stage: Rev. F Release 3.3-V 10Base-T/100Base-TX Integrated PHYceiver General Features The ICS1893BF is a low-power, physical-layer device (PHY) Supports category 5 cables with attenuation in excess of that supports the ISO/IEC 10Base-T and 100Base-TX 24dB at 100 MHz. Carrier-Sense Multiple Access/Collision Detection Single-chip, fully integrated PHY provides PCS, PMA, PMD, (CSMA/CD) Ethernet standards, ISO/IEC 8802-3. and AUTONEG sub layers functions of IEEE standard. The ICS1893BF is intended for MII, Node applications that require the Auto-MDIX feature that automatically corrects 10Base-T and 100Base-TX IEEE 8802.3 compliant crossover errors in plant wiring. Single 3.3V power supply The ICS1893BF incorporates Digital-Signal Processing (DSP) Highly configurable, supports: control in its Physical-Medium Dependent (PMD) sub layer. As Media Independent Interface (MII) a result, it can transmit and receive data on unshielded Auto-Negotiation with Parallel detection twisted-pair (UTP) category 5 cables with attenuation in Node applications, managed or unmanaged excess of 24 dB at 100MHz. With this ICS-patented 10M or 100M full and half-duplex modes technology, the ICS1893BF can virtually eliminate errors from Loopback mode for Diagnostic Functions killer packets. Auto-MDI/MDIX crossover correction The ICS1893BF provides a Serial-Management Interface for Low-power CMOS (typically 400 mW) exchanging command and status information with a Power-Down mode typically 21mW Station-Management (STA) entity. The ICS1893BF Media-Dependent Interface (MDI) can be configured to Clock and crystal supported provide either half- or full-duplex operation at data rates of 10 Fully integrated, DSP-based PMD includes: Mb/s or 100Mb/s. Adaptive equalization and baseline-wander correction The ICS1893BF is available in a 300-mil 48-lead SSOP Transmit wave shaping and stream cipher scrambler package. The ICS1893BF shares the same proven MLT-3 encoder and NRZ/NRZI encoder performance circuitry with the ICS1893AF but is not a Small footprint 48-pin 300 mil. SSOP package pin-for-pin replacement of the 1893AF. An application note for Also available in small footprint 56-pin 8x8 MLF2 package a dual footprint layout to accommodate ICS1893AF or ICS1893BF is available on the ICS website. Available in Industrial Temp Applications: NIC cards, PC motherboards, switches, routers, DSL and cable modems, game machines, printers. ICS1893BF Block Diagram 100Base-T PCS PMA TP PMD Framer Clock Recovery MLT-3 10/100 MII Twisted- Interface Integrated CRS/COL Link Monitor Stream Cipher MAC Detection Signal Detection Adaptive Equalizer Pair MUX Switch Interface Parallel to Serial Error Detection Baseline Wander Interface to 4B/5B Correction Magnetics Modules and 10Base-T RJ45 Connector MII Low-Jitter Auto- Configuration Extended MII Clock Negotiation and Status Register Management Synthesizer Set Interface Clock Power LEDs and PHY Address ICS1893BF, Rev. F, 5/13/10 IDT reserves the right to make changes in the device data identified in May, 2010 this publication without further notice. IDT advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.ICS1893BF Data Sheet - Release Table of Contents Table of Contents Section Title Page Chapter 1 Abbreviations and Acronyms .........................................................................................10 Chapter 2 Conventions and Nomenclature.....................................................................................12 Chapter 3 Overview of the ICS1893BF.............................................................................................14 3.1 100Base-TX Operation ..........................................................................................15 3.2 10Base-T Operation ...............................................................................................15 Chapter 4 Operating Modes Overview.............................................................................................16 4.1 Reset Operations ...................................................................................................17 4.1.1 General Reset Operations .....................................................................................17 4.1.2 Specific Reset Operations .....................................................................................18 4.2 Power-Down Operations ........................................................................................19 4.3 Automatic Power-Saving Operations .....................................................................20 4.4 Auto-Negotiation Operations ..................................................................................20 4.5 100Base-TX Operations ........................................................................................21 4.6 10Base-T Operations .............................................................................................21 4.7 Half-Duplex and Full-Duplex Operations ...............................................................21 4.8 Auto-MDI/MDIX Crossover .....................................................................................22 Chapter 5 Interface Overviews..........................................................................................................23 5.1 MII Data Interface ..................................................................................................24 5.2 Serial Management Interface .................................................................................25 5.3 Twisted-Pair Interface ............................................................................................25 5.3.1 Twisted-Pair Transmitter.........................................................................................25 5.4 Clock Reference Interface .....................................................................................27 5.5 Status Interface ......................................................................................................29 Chapter 6 Functional Blocks.............................................................................................................31 6.1 Functional Block: Media Independent Interface .....................................................32 6.2 Functional Block: Auto-Negotiation ........................................................................33 6.2.1 Auto-Negotiation General Process ........................................................................33 6.2.2 Auto-Negotiation: Parallel Detection ......................................................................34 6.2.3 Auto-Negotiation: Remote Fault Signaling .............................................................35 6.2.4 Auto-Negotiation: Reset and Restart .....................................................................35 6.2.5 Auto-Negotiation: Progress Monitor .......................................................................36 ICS1893BF, Rev. F, 5/13/10 May, 2010 Copyright 2009, IDT, Inc. All rights reserved. 2