HCF4029B PRESETTABLE UP/DOWN COUNTER BINARY OR BCD DECADE MEDIUM SPEED OPERATION : 8MHz (Typ.) at C = 50pF and V - V = 10V L DD SS MULTI-PACKAGE PARALLEL CLOCKING FOR SYNCHRONOUS HIGH SPEED OUTPUT RESPONSE OR RIPPLE CLOCKING FOR SLOW CLOCK INPUT RISE AND FALL TIMES DIP SOP PRESET ENABL AND INDIVIDUALJA INPUTS PROVIDED BINARY OR DECADE UP/DOWN ORDER CODES COUNTING PACKAGE TUBE T & R BCD OUTPUTS IN DECADE MODE DIP HCF4029BEY QUIESCENT CURRENT SPECIF. UP TO 20V SOP HCF4029BM1 HCF4029M013TR STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS INPUT LEAKAGE CURRENT inputs consist of a single CLOCK, CARRY IN I = 100nA (MAX) AT V = 18V T = 25C I DD A (CLOCK ENABLE), BINARY/DECADE, UP/ 100% TESTED FOR QUIESCENT CURRENT DOWN, PRESET ENABLE, and four individual MEETS ALL REQUIREMENTS OF JEDEC JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT JESD13BSTANDARD SPECIFICATIONS signal are provided as outputs. A high PRESET FOR DESCRIPTION OF B SERIES CMOS ENABLE signal allows information on the JAM DEVICE INPUTS to preset the counter to any state asynchronously with the clock. A low on each JAM DESCRIPTION line, when the PRESET-ENABLE signal is high, HCF4029B is a monolithic integrated circuit resets the counter to its zero count. The counter fabricated in Metal Oxide Semiconductor advances one count at the positive transition of technology available in DIP and SOP packages. the clock when the CARRY-IN and PRESET HCF4029B consists of a four stage binary or ENABLE signals are low. Advancement is BCD-decade up/down counter with provisions for inhibited when the CARRY-IN or PRESET look ahead carry in both counting modes. The ENABLE signals are high. The CARRY-OUT PIN CONNECTION September 2002 1/12HCF4029B signal is normally high and the counter reaches its counter counts Up when to UP/DOWN INPUT is maximum count in the UP mode or the minimum high, and Down when the UP/DOWN INPUT is count in the DOWN mode provided the CARRY-IN low. Multiple packages can be connected in either signal is low. The CARRY-IN signal in the low a parallel clocking or a ripple clocking state can thus be considered a CLOCK ENABLE. arrangement. Parallel clocking provides The CARRY-IN terminal must be connected to synchronous control and, hence, a faster V when not in use. Binary counting is SS response from all counting outputs. Ripple accomplished when the BINARY/DECODE input clocking allows for longer clock input rise and fall is high the counter counts in the decade mode when the BINARY/DECADE input is low. The times. IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 15 CLOCK Clock Input 5 CARRY IN Carry In Input BINARY/ 9 Binary / Decade Select DECADE 10 UP/DOWN Up/Down Select PRESET 1 Preset Enable Input ENABLE 4, 12, 13, 3 JAM1 to JAM4 Jam Input Signals 6, 11, 14, 2 Q1 to Q4 Q Outputs 7 CARRY OUT Carry Out Outputs 8 V Negative Supply Voltage SS V 16 Positive Supply Voltage DD FUNCTIONAL DIAGRAM 2/12