HCF4042B QUAD CLOCKED D LATCH CLOCK POLARITY CONTROL Q AND Q OUTPUTS COMMON CLOCK LOW POWER TTL COMPATIBLE STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS DIP SOP QUIESCENT CURRENT SPECIFIED UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS ORDER CODES INPUT LEAKAGE CURRENT PACKAGE TUBE T & R I = 100nA (MAX) AT V = 18V T = 25C I DD A DIP HCF4042BEY 100% TESTED FOR QUIESCENT CURRENT SOP HCF4042BM1 HCF4042M013TR MEETS ALL REQUIREMENTS OF JEDEC JESD13B STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS Information present at the data input is transferred DEVICE to outputs Q and Q during the CLOCK level which is programmed by the POLARITY input. For DESCRIPTION POLARITY = 0 the transfer occurs during the 0 The HCF4042B is a monolithic integrated circuit CLOCK level and for POLARITY = 1 the transfer fabricated in Metal Oxide Semiconductor occurs during the 1 CLOCK level. The outputs technology available in DIP and SOP packages. follow the data input providing the CLOCK and The HCF4042B types contains four latch circuit, POLARITY levels defined above are present. each strobes by a common clock. Complementary When a CLOCK transition occurs (positive for buffered outputs are available from each circuit. POLARITY = 0 and negative for POLARITY = 1) The impedance of the n and p channel output the information present at the input during the devices is balanced and all outputs are electrically CLOCK transition is retained at the outputs until identical. an opposite CLOCK transition occurs. PIN CONNECTION September 2001 1/9HCF4042B IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 4, 7, 13, 14 D1 to D4 Data Inputs 2, 10, 11, 1 Q1 to Q4 Q outputs 3, 9, 12, 15 Q1 to Q4 Q outputs 5 CLOCK Clock Input 6 POLARITY Polarity inputs 8 V Negative Supply Voltage SS V 16 Positive Supply Voltage DD FUNCTIONAL DIAGRAM TRUTH TABLE CLOCK POLARITY Q L0 D 0LATCH H1 D 1LATCH 2/9