HCF4099B 8 BIT ADDRESSABLE LATCH SERIAL DATA INPUT - ACTIVE PARALLEL OUTPUT STORAGE REGISTER CAPABILITY - MASTER CLEAR CAN FUNCTION AS DEMULTIPLEXER QUIESCENT CURRENT SPECIFIED UP TO DIP SOP 20V STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS INPUT LEAKAGE CURRENT ORDER CODES I = 100nA (MAX) AT V = 18V T = 25C I DD A PACKAGE TUBE T & R 100% TESTED FOR QUIESCENT CURRENT DIP HCF4099BEY MEETS ALL REQUIREMENTS OF JEDEC SOP HCF4099BM1 HCF4099M013TR JESD13BSTANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICE WRITE DISABLE is high, data entry is inhibited DESCRIPTION however, all 8 outputs can be continuously read HCF4099B is a monolithic integrated circuit independent of WRITE DISABLE and address fabricated in Metal Oxide Semiconductor inputs. A master RESET input is available, which technology available in DIP and SOP packages. resets all bits to a logic0 level when RESET and HCF4099B, an 8-bit addressable latch, is a WRITE DISABLE are at a high level. When serial-input, parallel output storage register that RESET is at a high level, and WRITE DISABLE is at a low level, the latch acts as a 1-of-8 can perform a variety of functions. Data is input to a particular bit in the latch when that bit is demultiplexer the bit that is addressed has an addressed (by means of input A0, A1, A2) and active output which follows the data input, while all when WRITE DISABLE is at a low level. When unaddressed bits are held to a logic0 level. PIN CONNECTION October 2002 1/14 Obsolete Product(s) - Obsolete Product(s)HCF4099B IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 5, 6, 7 A0 to A2 Address Inputs 9, 10, 11, 12, Q0 to Q7 Latch Outputs 13, 14, 15, 1 3 DATA Data Inputs 2 RESET Reset Input WRITE 4 Write Disable Input DISABLE V 8 Negative Supply Voltage SS V 16 Positive Supply Voltage DD FUNCTIONAL DIAGRAM TRUTH TABLE SELECT INPUTS LATCH ADDRESSED CBA LLL Q0 LL H Q1 LHL Q2 LH H Q3 HL L Q4 HLH Q5 HH L Q6 HHH Q7 INPUTS OUTPUTS OF EACH OTHER ADDRESSED FUNCTION OUTPUT WRITE DISABLE RESET LATCH L L D Qi0 ADDRESSABLE LATCH L H Qi0 Qi0 MEMORY H L D L DEMULTIPLEXER H H L L CLEAR ALL BITS TO0 D: The level at the data input Q The level before the indicated steady state input conditions were established, (i=0, 1,...7) i0 2/14 Obsolete Product(s) - Obsolete Product(s)