TC74HC259AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC259AP, TC74HC259AF 8-Bit Addressable Latch The TC74HC259A is a high speed CMOS ADDRESSABLE 2 TC74HC259AP LATCH fabricated with silicon gate C MOS technology. It achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The respective bits are controlled by address inputs A, B, and C. When CLEAR input is held high and enable input G is held low, the data is written into the bit selected by address inputs, the other bit hold their previous conditions. When both CLEAR and G held high, writing of all bits is inhibited regardless of adress inputs, and their previous condition are held. When CLEAR is held low and G is held TC74HC259AF high, all bits are resent to low regardless of the other inputs. When both of CLEAR and G held low, all bits which isnt selected by adress inputs are resent to low. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features High speed: t = 15 ns (typ.) at V = 5 V pd CC Low power dissipation: I = 4 A (max) at Ta = 25C CC High noise immunity: V = V = 28% V (min) NIH NIL CC Weight DIP16-P-300-2.54A : 1.00 g (typ.) Output drive capability: 10 LSTTL loads SOP16-P-300-1.27A : 0.18 g (typ.) Symmetrical output impedance: I = I = 4 mA (min) OH OL Balanced propagation delays: t t pLH pHL Wide operating voltage range: V (opr) = 2 to 6 V CC Pin and function compatible with 74LS259 Pin Assignment Start of commercial production 1988-05 1 2014-03-01 TC74HC259AP/AF IEC Logic Symbol Truth Table Output of Inputs Each Other Addressed Function Output CLEAR G Latch H L D QiO Addressable Latch H H QiO QiO Memory L L D L 8-Line Demultriplexer L H L L Clear All Bits to L Select Inputs Latch Addressed C B A L L L Q0 L L H Q1 L H L Q2 L H H Q3 H L L Q4 H L H Q5 H H L Q6 H H H Q7 D: The level at the data input. QiO: The level before the indicared steady-state input conditions were established (i = 0, 1, ....7) 2 2014-03-01