TC74HC279AF(F) Toshiba

TC74HC279AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC279AP, TC74HC279AF Quad S-R Latch The TC74HC279A is a high speed CMOS QUAD S-R LATCH 2 TC74HC279AP fabricated with silicon gate C MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. Each latch has an independent Q output and Set and Reset inputs. S and R are active low. When S input is low, the Q output goes high and when R input is low, the Q output goes low. When both S and R are low, S takes precedence resulting Q = low. When both of S and R are held high, Q output doesnt change. All inputs are equipped with protection circuits against static TC74HC279AF discharge or transient excess voltage. Features High speed: t = 12 ns (typ.) at V = 5 V pd CC Low power dissipation: I = 2 A (max) at Ta = 25C CC High noise immunity: V = V = 28% V (min) NIH NIL CC Symmetrical output impedance: I = I = 4 mA (min) OH OL Balanced propagation delays: t t pLH pHL Weight Wide operating voltage range: V (opr) = 2 to 6 V CC DIP16-P-300-2.54A : 1.00 g (typ.) Pin and function compatible with 74LS279 SOP16-P-300-1.27A : 0.18 g (typ.) Pin Assignment Start of commercial production 1988-05 1 2014-03-01 TC74HC279AP/AF IEC Logic Symbol (2) & 1S1 S1 (4) (3) 1 1Q 1S2 (1) R 1R (6) S2 2S (7) (5) 2 2Q 2R R (11) 3S1 & (12) S3 (9) 3S2 3 3Q (10) 3R R (15) 4S S4 (13) 4 4Q (14) 4R R Truth Table Inputs Output S R Q H H Qn L H H H L L L L H Qn: The level of Q before the indicated input condition were established. : For latches with doubles S input. H = Both S input high L = One of both inputs low System Diagram 2 2014-03-01