TC74HCT373AF(F) Toshiba

TC74HCT373AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HCT373AP, TC74HCT373AF Octal D-Type Latch with 3-State Output The TC74HCT373A is a high speed CMOS OCTAL LATCH 2 TC74HCT373AP with 3-STATE OUTPUT fabricated with silicon gate C MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. Their inputs are compatible with TTL, NMOS, and CMOS output voltage levels. These 8-bit D-type latches are controlled by a latch enable input (LE) and an output enable input ( OE ). When the OE input is high, the eight outputs are in a high impedance state. TC74HCT373AF All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features High speed: t = 17 ns (typ.) at V = 5 V pd CC Low power dissipation: I = 4 A (max) at Ta = 25C CC Compatible with TTL outputs: V = 2 V (min) IH V = 0.8 V (max) IL Weight Wide interfacing ability: LSTTL, NMOS, CMOS DIP20-P-300-2.54A : 1.30 g (typ.) Output drive capability: 15 LSTTL loads SOP20-P-300-1.27A : 0.22 g (typ.) Symmetrical output impedance: I = I = 6 mA (min) OH OL Balanced propagation delays: t t pLH pHL Pin and function compatible with 74LS373 Pin Assignment Start of commercial production 1988-11 1 2014-03-01 TC74HCT373AP/AF IEC Logic Symbol Truth Table Inputs Output OE LE D Q H X X Z L L X Qn L H L L L H H H X: Dont care Z: High impedance Qn: Q outputs are latched at the time when the LE input is taken to a low logic level. System Diagram 2 2014-03-01