L6574 CFL/TL BALLAST DRIVER PREHEAT AND DIMMING HIGH VOLTAGE RAIL UP TO 600V dV/dt IMMUNITY 50 V/ns IN FULL TEMPERATURE RANGE DRIVER CURRENT CAPABILITY: 250mA SOURCE 450mA SINK SO16N DIP16 SWITCHING TIMES 80/40ns RISE/FALL ORDERING NUMBERS: WITH 1nF LOAD L6574D L6574 CMOS SHUT DOWN INPUT UNDER VOLTAGE LOCK OUT PREHEAT AND FREQUENCY SHIFTING The device is intended to drive two power MOS- TIMING FETS, in the classical half bridge topology, ensur- SENSE OP AMP FOR CLOSED LOOP ing all the features needed to drive and properly CONTROL OR PROTECTION FEATURES control a fluorescent bulb. HIGH ACCURACY CURRENT CONTROLLED A dedicated timing section in the L6574 allows the OSCILLATOR user set the necessary parameters for proper pre- INTEGRATED BOOTSTRAP DIODE heat and ignition of the lamp. CLAMPING ON VS. Also, an OP AMP is available to implement closed SO16, DIP 16 PACKAGES loop control of the lamp current during normal lamp burning. DESCRIPTION An integrated bootstrap section, eliminating the nor- mally required bootstrap diode and the zener clamp- In order to ensure voltage ratings in excess of ing on Vs, makes the L6574 well suited for low cost 600V, the L6574 is manufactured with BCD OFF applications where few additional components are LINE technology, which makes it well suited for needed to build a high performance ballast. lamp ballast applications. BLOCK DIAGRAM H.V. V S OP AMP V BOOT + OPOUT - BOOTSTRAP HVG UV HVG OPIN- C BOOT DRIVER DETECTION DRIVER OPIN+ LOAD OUT Imin V REF LEVEL V S DEAD DRIVING SHIFTER TIME LOGIC LVG Ifs Ipre LVG DRIVER R ING Imax V GND REF + Vthpre - V THE + R - EN1 PRE + CONTROL LOGIC - V THE + - EN2 VCO Cf D97IN493A C PRE September 2003 1/10L6574 PIN CONNECTION (top view) CPRE 1 16 VBOOT RPRE 2 15 HVG CF 3 14 OUT RING 4 13 N.C. OPOUT 5 12 V S OPIN- 6 11 LVG OPIN+ 7 10 GND EN1 8 9 EN2 D97IN492 THERMAL DATA Symbol Parameter DIP16 SO16N Unit R Thermal Resistance Junction to ambient Max. 80 120 C/W th j-amb PIN DESCRIPTION N Pin Function 1 CPRE Preheat Timing Capacitor. The capacitor C sets the preheating and the frequency shift time, PRE according to the relations: t = K C and t = K C (typ. K = 1.5s/F, K = PRE PRE PRE SH FS PRE PRE FS 0.15s/F). This feature is obtained by charging CPRE with two different currents. During tPRE this current is independent of the external components, so CPRE is charged up to 3.5V (preheat the current depends on R value (i.e. on the differ- timing comparator threshold). During t SH PRE ence between f and f ). In this way t is always set at 0.1t . In steady state the voltage PRE IGN SH PRE at pin 1 is 5V. 2 RPRE Maximum Oscillation Frequency Setting. The resistance connected between this pin and ground sets the fPRE value, fixing the difference between f and f (f > f ). At the end of the PRE IGN PRE IGN Start-up procedure, the effect current drown from R is over. The voltage at this pin is fixed at PRE V =2V. REF 3 CF Oscillator Frequency Setting. The capacitor C , along with to R and R , sets f and f . F PRE IGN PRE ING In normal operation this pin shows a triangular wave. 4 RIGN Minimum Oscillation Frequency Setting. The resistance connected between this pin and ground sets the f value. The voltage at this pin is fixed at V =2V. IGN REF 5 OPout Out of the operational amplifier. To implement a feedback control loop this pin can be connected to the RIGN pin by means an appropriate circuitry. 6 OPin- Inverting Input of the operational amplifier. 7 OPin+ Non Inverting Input of the operational amplifier. 8 EN1 Enable 1. This pin (active high), forces the device in a latched shutdown state (like in the under voltage conditions). There are two ways to resume normal operation: the first is to reduce the supply voltage below the undervoltage threshold and then increase it again until the valid supply is recognised. the second is activating EN2 input. The enable 1 is especially designed for strong fault (e.g. in case of lamp disconnection). 2/10