L6740LTR STMicroelectronics

L6740L Hybrid controller (4+1) for AMD SVID and PVID processors Features Hybrid controller: compatible with PVI and SVI CPUs Dual controller: 2 to 4 scalable phases for CPU CORE, 1 phase for NB Dual-edge asynchronous architecture with HTQFP48 tm LTB Technology PSI management to increase efficiency in Description light-load conditions L6740L is a hybrid CPU power supply controller Dual over-current protection: compatible with both parallel (PVI) and serial Average and per-phase (SVI) protocols for AMD processors. Load indicator (CORE section) The device embeds two independent control Logic level support for LVDDRIII loops for the CPU core and the integrated NB, Voltage positioning each one with its own set of protections. L6740L Dual remote sense is able to work in single-plane mode, addressing only the CORE section, according to the parallel Adjustable independent reference offset DAC codification. When in dual-plane mode, it is Feedback disconnection protection compatible with the AMD SVI specification Programmable OV protection addressing the CPU and NB voltages according to the SVI bus commands. Oscillator internally fixed at 150 kHz externally adjustable The dual-edge asynchronous architecture is opti- tm mized by LTB Technology allowing fast load- LSLess startup to manage pre-biased output transient response minimizing the output capaci- Flexible driver support tor and reducing the total BOM cost. HTQFP48 package PSI management allows the device to selectively turn-off phases when the CPU is in low-power Applications states increasing the over-all efficiency. Hybrid high-current VRM, VRD for desktop, Fast protection against load over current is pro- server, workstation, IPC CPUs supporting PVI vided for both the sections. Furthermore, and SVI interface feedback disconnection protection prevents from damaging the load in case of disconnections in High-density DC / DC converters the system board. Table 1. Device summary Order codes Package Packaging L6740L HTQFP48 Tube L6740LTR HTQFP48 Tape and reel September 2008 Rev 3 1/44 www.st.com 1Contents L6740L Contents 1 Typical application circuit and block diagram 4 1.1 Application circuit 4 1.2 Block diagram . 7 2 Pins description and connection diagrams 8 2.1 Pin descriptions . 8 2.2 Thermal data 12 3 Electrical specifications . 13 3.1 Absolute maximum ratings 13 3.2 Electrical characteristics 13 4 Device description and operation . 15 5 Hybrid CPU support and CPU TYPE detection 16 5.1 PVI - parallel interface . 16 5.2 PVI start-up . 16 5.3 SVI - serial interface . 18 5.4 SVI start-up . 18 5.4.1 Set VID command . 18 5.4.2 PWROK de-assertion 21 5.4.3 PSI L and efficiency optimization at light-load . 21 5.4.4 HiZ management 22 5.4.5 Hardware jumper override - V FIX 22 6 Output voltage positioning . 23 6.1 CORE section - phase programming 24 6.2 CORE section - current reading and current sharing loop 24 6.3 CORE section - load-line and load-indicator (optional) 25 6.4 CORE section - offset (optional) 26 6.5 NB section - current reading . 26 6.6 NB section - load-line and load-indicator (optional) . 27 6.7 NB section - offset (optional) 27 2/44