L9963T-TR STMicroelectronics

L9963T Datasheet Automotive general purpose SPI to isolated SPI transceiver Features AEC-Q100 qualified Full ISO26262 compliant, ASIL-D systems ready Compatible with both 3.3 V and 5 V logics Supports both XFMR and Capacitive isolation 10 MHz SPI peripheral for SPI Slave operation. Configurable SPI frequency (250 kHz to 8 MHz) for SPI Master operation 333 kbps and 2.66 Mbps Vertical InterFace (VIF) for isolated SPI communication Low standby current Application Automotive: 48 V and high-voltage systems Backup energy storage systems and UPS Industrial communication networks Portable and semi-portable equipment Remote sensors Description L9963T is a general purpose SPI to isolated SPI transceiver intended to create a communication bridge between devices located into different voltage domains. Product status link L9963T is able to transfer communication data incoming from a classical 4-wire L9963T based SPI interface to a 2-wire isolated interface (and viceversa). Product summary The transceiver supports both transformer and capacitive isolation, since the isolated signal generated according to a propetary protocol is suitable to be transmitted over Order code Package Packing both decoupling circuitries. L9963T Tube SO16N The device can be configured either as Slave or as Master of the SPI bus and L9963T-TR Tape&Reel supports any protocol made of SPI frames 8 to 64 bit long. The transceiver manages the transfer of the information without performing any protocol check. Product label SPI peripheral can work up to 10 MHz when configured as Slave. SPI clock frequency can be programmed among (250 kHz 1 MHz 4 MHz 8 MHz) when configured as Master. Isolated SPI peripheral features two different operating modes: slow 333 kbps and fast 2.66 Mbps. The asynchronicity between the two sides is internally managed, allowing all possible configuration frequencies on both peripherals to be used in application. L9963T features an internal queue of 3 slots for the frames received on the SPI port and a queue of 20 slots for the ones received on the isolated SPI side. This allows buffering and decoupling the two different clock domains. The device is natively compatible with L9963 isolated SPI, allowing its usage in the BMS applications. L9963T is compatible with both 3.3 V and 5 V logics. DS13590 - Rev 1 - January 2021 www.st.com For further information contact your local STMicroelectronics sales office.L9963T Block diagram and pin description 1 Block diagram and pin description 1.1 Block diagram Figure 1. Block diagram 1.2 Pin description Figure 2. Pin connection diagram (top view) Digital 1 16 VIO VDD Analog 2 15 SDO ISOP Power 14 3 GND ISOM SCK 4 13 SDI GND 5 12 NCS NSLAVE 6 11 DIS TXEN/CPHA 7 10 ISOFREQ SPICLKFREQ 8 9 BNE/CPOL TXAMP DS13590 - Rev 1 page 2/46