LD39200PU33R STMicroelectronics

LD39200 Datasheet 2 A high PSRR ultra low drop linear regulator with reverse current protection Features Input voltage from 1.25 V to 6.0 V Ultra low drop: 130 mV (typ.) at 2 A load 1 % output accuracy at 25 C, 2 % in full temperature range High PSRR: 70 dB at 1 kHz Reverse current protection 2 A guaranteed output current Available in fixed and adjustable output voltage version from 0.5 V with 100 mV step Power Good Internal current and thermal limit Operating junction temperature range: -40 C to 125 C DFN6 (3 x 3 mm) and DFN8 (4 x 4 mm) packages Applications Telecom infrastructure Medium power POL Description The LD39200 provides 2 A of maximum current with an input voltage range from 1.25 V to 6.0 V, and a typical dropout voltage of 130 mV. Maturity status link It is stable with ceramic capacitors on the output (10 F). LD39200 Typical power supply rejection ratio is 70 dB at 1 kHz and starts to roll off at 20 kHz. The enable logic control function puts the LD39200 in shutdown mode, reducing the total current consumption to 10 nA (typ.). Power Good flag is available on a dedicated pin. The device also includes reverse current protection, short-circuit constant current limit and thermal protection. Typical applications are for Telecom infrastructure and consumer. DS10079 - Rev 3 - September 2018 www.st.com For further information contact your local STMicroelectronics sales office.LD39200 Block diagram 1 Block diagram Figure 1. Block diagram VIN Power good VREF PG VFB RC filter R1 Bandgap reference Reverse 500mV 500mV current protection OPAMP R2 VFB PMOS VOUT R3 Internal EN enable Enable R4 AM13907V1 DS10079 - Rev 3 page 2/29