M74HC139 DUAL 2 TO 4 DECODER/DEMULTIPLEXER HIGH SPEED: t = 13ns (TYP.) at V = 6V PD CC LOW POWER DISSIPATION: I = 4A(MAX.) at T =25C CC A HIGH NOISE IMMUNITY: V = V = 28 % V (MIN.) NIH NIL CC DIP SOP TSSOP SYMMETRICAL OUTPUT IMPEDANCE: I = I = 4mA (MIN) OH OL BALANCED PROPAGATION DELAYS: t t ORDER CODES PLH PHL WIDE OPERATING VOLTAGE RANGE: PACKAGE TUBE T & R V (OPR) = 2V to 6V CC DIP M74HC139B1R PIN AND FUNCTION COMPATIBLE WITH SOP M74HC139M1R M74HC139RM13TR 74 SERIES 139 TSSOP M74HC139TTR DESCRIPTION The M74HC139 is an high speed CMOS QUAD While the enable input is held high, all four outputs 2-INPUT NAND GATE fabricated with silicon gate are high independently of the other inputs. 2 C MOS technology. All inputs are equipped with protection circuits The active low enable input can be used for gating against static discharge and transient excess or as a data input for demultiplexing applications. voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/9M74HC139 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1, 15 1G, 2G Enable Inputs 2, 3 1A, 1B Address Inputs 4, 5, 6, 7 1Y TO 1Y Outputs 0 3 2Y TO 2Y 12, 11, 10, 9 Outputs 0 3 14, 13 2A, 2B Address Inputs 8 GND Ground (0V) V 16 Positive Supply Voltage CC TRUTH TABLE INPUTS OUTPUTS SELECTED ENABLE SELECT OUTPUT Y Y Y Y 0 1 2 3 G BA H X X H H H H NONE Y L LLL H H H 0 Y LL HH LHH 1 Y LH L HH L H 2 Y L HHHH H L 3 LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/9