M74HC174 HEX D-TYPE FLIP FLOP WITH CLEAR HIGH SPEED : f = 66MHz (TYP.) at V = 6V MAX CC LOW POWER DISSIPATION: I =4A(MAX.) at T =25C CC A HIGH NOISE IMMUNITY: V = V = 28 % V (MIN.) NIH NIL CC DIP SOP TSSOP SYMMETRICAL OUTPUT IMPEDANCE: I = I = 4mA (MIN) OH OL BALANCED PROPAGATION DELAYS: t t PLH PHL ORDER CODES WIDE OPERATING VOLTAGE RANGE: PACKAGE TUBE T & R V (OPR) = 2V to 6V CC DIP M74HC174B1R PIN AND FUNCTION COMPATIBLE WITH SOP M74HC174M1R M74HC174RM13TR 74 SERIES 174 TSSOP M74HC174TTR DESCRIPTION The M74HC174 is an high speed CMOS HEX held low, the Q outputs are held low independently D-TYPE FLIP FLOP WITH CLEAR fabricated with of the other inputs. 2 silicon gate C MOS technology. All inputs are equipped with protection circuits Information signals applied to D inputs are against static discharge and transient excess transferred to the Q output on the positive going voltage. edge of the clock pulse. When the CLEAR input is PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/11M74HC174 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION Asynchronous Master 1 CLEAR Reset (Active Low) 2, 5, 7, 10, Q0 to Q5 Flip-Flop Outputs 12, 15 3, 4, 6, 11, D0 to D5 Data Inputs 13, 14 Clock Input (LOW to 9 CLOCK HIGH, edge triggered) 8 GND Ground (0V) 16 Vcc Positive Supply Voltage TRUTH TABLE INPUTS OUTPUTS FUNCTION CLEAR DCK Q L X X L CLEAR HL L HH H H X Qn NO CHANGE X : Dont Care LOGIC DIAGRAM This logic diagram has not to be used to estimate propagation delays 2/11