DM74ALS273 Octal D-Type Edge-Triggered Flip-Flop with Clear April 1984 Revised February 2000 DM74ALS273 Octal D-Type Edge-Triggered Flip-Flop with Clear General Description Features These monolithic, positive-edge-triggered flip-flops utilize Switching specifications at 50 pF TTL circuitry to implement D-type flip-flop logic with a direct Switching specifications guaranteed over full tempera- clear input. ture and V range CC Information at the D inputs meeting the setup requirements Buffer-type outputs and improved AC offer significant is transferred to the Q outputs on the positive-going edge advantage over DM74LS273. of the clock pulse. Clock triggering occurs at a particular Advanced oxide-isolated, ion-implanted Schottky TTL voltage level and is not directly related to the transition time process of the positive-going pulse. When the clock input is at Functionally and pin-for-pin compatible with either the HIGH or LOW level, the D input signal has no DM74LS273. effect at the output. Ordering Code: Order Number Package Number Package Description DM74ALS273WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74ALS273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74ALS273MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide DM74ALS273N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Connection Diagram 2000 Fairchild Semiconductor Corporation DS006216 www.fairchildsemi.comFunction Table Logic Diagram (Each Flip-Flop) Inputs Output Clear Clock D Q LX X L H HH H LL HL X Q 0 L = LOW State H = HIGH State X = Dont Care = Positive Edge Transition Q = Previous Condition of Q 0 www.fairchildsemi.com 2 DM74ALS273