74AC273, 74ACT273 Octal D-Type Flip-Flop January 2008 74AC273, 74ACT273 Octal D-Type Flip-Flop Features General Description Ideal buffer for microprocessor or memory The AC273 and ACT273 have eight edge-triggered D-type flip-flops with individual D-type inputs and Q Eight edge-triggered D-type flip-flops outputs. The common buffered Clock (CP) and Master Buffered common clock Reset (MR) input load and reset (clear) all flip-flops Buffered, asynchronous master reset simultaneously. See 377 for clock enable version The register is fully edge-triggered. The state of each See 373 for transparent latch version D-type input, one setup time before the LOW-to-HIGH See 374 for 3-STATE version clock transition, is transferred to the corresponding flip- Outputs source/sink 24mA flop s Q output. 74ACT273 has TTL-compatible inputs All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. Ordering Information Package Order Number Number Package Description 74AC273SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74AC273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC273PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74ACT273SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ACT273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. 1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74AC273, 74ACT273 Rev. 1.6.074AC273, 74ACT273 Octal D-Type Flip-Flop Connection Diagram Logic Symbols IEEE/IEC Pin Description Pin Names Description D D Data Inputs 0 7 MR Master Reset CP Clock Pulse Input Q Q Data Outputs 0 7 Mode Select-Function Table Inputs Outputs Operating Mode MR CP D Q n n Reset (Clear) L X X L Load 1 H H H Load 0 H L L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74AC273, 74ACT273 Rev. 1.6.0 2