74AC374, 74ACT374 Octal D-Type Flip-Flop with 3-STATE Outputs
January 2008
74AC374, 74ACT374
Octal D-Type Flip-Flop with 3-STATE Outputs
Features General Description
I and I reduced by 50% The AC/ACT374 is a high-speed, low-power octal D-type
CC OZ
flip-flop featuring separate D-type inputs for each flip-flop
Buffered positive edge-triggered clock
and 3-STATE outputs for bus-oriented applications. A
3-STATE outputs for bus-oriented applications
buffered Clock (CP) and Output Enable (OE) are com-
Outputs source/sink 24mA
mon to all flip-flops.
See 273 for reset version
See 377 for clock enable version
See 373 for transparent latch version
See 574 for broadside pinout version
See 564 for broadside pinout version with inverted
outputs
ACT374 has TTL-compatible inputs
Ordering Information
Order Package
Number Number Package Description
74AC374SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74AC374SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC374MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74AC374PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74ACT374SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ACT374SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT374MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
74ACT374MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74ACT374PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC374, 74ACT374 Rev. 1.5.074AC374, 74ACT374 Octal D-Type Flip-Flop with 3-STATE Outputs
Connection Diagram
Logic Symbols
IEEE/IEC
Pin Description
Pin
Names Description
D D Data Inputs
0 7
CP Clock Pulse Input
OE 3-STATE Output Enable Input
O O 3-STATE Outputs
0 7
Truth Table
Functional Description
Inputs Outputs
The AC/ACT374 consists of eight edge-triggered flip-
D CP OE O
n n
flops with individual D-type inputs and 3-STATE true out-
puts. The buffered clock and buffered Output Enable are
HL H
common to all flip-flops. The eight flip-flops will store the
LL L
state of their individual D inputs that meet the setup and
XX H Z
hold time requirements on the LOW-to-HIGH Clock (CP)
transition. With the Output Enable (OE) LOW, the con-
H = HIGH Voltage Level
tents of the eight flip-flops are available at the outputs.
L = LOW Voltage Level
When the OE is HIGH, the outputs go to the high imped-
X = Immaterial
ance state. Operation of the OE input does not affect the
state of the flip-flops.
Z = High Impedance
= LOW-to-HIGH Transition
1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC374, 74ACT374 Rev. 1.5.0 2