74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop
March 2007
74AC109, 74ACT109
tm
Dual JK Positive Edge-Triggered Flip-Flop
Features General Description
I reduced by 50% The AC/ACT109 consists of two high-speed completely
CC
flip-flops. The clocking
independent transition clocked JK
Outputs source/sink 24mA
operation is independent of rise and fall times of the
ACT109 has TTL-compatible inputs
clock waveform. The JK design allows operation as a
D-Type flip-flop (refer to AC/ACT74 data sheet) by
connecting the J and K inputs together.
Asynchronous Inputs:
(Set) sets Q to HIGH level
LOW input to S
D
LOW input to C
(Clear) sets Q to LOW level
D
Clear and Set are independent of clock
Simultaneous LOW on C
and S makes both
D D
Q and Q HIGH
Ordering Information
Order Package
Number Number Package Description
74AC109SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74AC109SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC109MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74ACT109SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74AC109MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74ACT109PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number.
Connection Diagram Pin Descriptions
Pin Names Description
J , J , K , K Data Inputs
1 2 1 2
, CP Clock Pulse Inputs
CP
1 2
C , C Direct Clear Inputs
D1 D2
S , S Direct Set Inputs
D1 D2
, Q , Q , Q Outputs
Q
1 2 1 2
FACT is a trademark of Fairchild Semiconductor Corporation.
1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC109, 74ACT109 Rev. 1.574AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop
Logic Symbols
IEEE/IEC
Truth Table
Each half.
Inputs Outputs
S C CP J K Q Q
D D
LH X X X H L
HL X X X L H
LL X X X H H
HH L L L H
HH HL Toggle
HH L H Q Q
0 0
HH H H H L
HH L X X Q Q
0 0
H = HIGH Voltage Level
L = LOW Voltage Level
= LOW-to-HIGH Transition
X = Immaterial
Q (Q ) = Previous Q (Q ) before LOW-to-HIGH Transition of Clock
0 0 0 0
Logic Diagram
One half shown.
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC109, 74ACT109 Rev. 1.5 2