74AC377, 74ACT377 Octal D-Type Flip-Flop with Clock Enable
January 2008
74AC377, 74ACT377
Octal D-Type Flip-Flop with Clock Enable
Features General Description
I reduced by 50% The AC/ACT377 has eight edge-triggered, D-type flip-
CC
flops with individual D inputs and Q outputs. The com-
Ideal for addressable register applications
mon buffered Clock (CP) input loads all flip-flops simulta-
Clock enable for address and data synchronization
neously, when the Clock Enable (CE) is LOW.
applications
Eight edge-triggered D-type flip-flops The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock
Buffered common clock
transition, is transferred to the corresponding flip-flop's Q
Outputs source/sink 24mA
output. The CE input must be stable only one setup time
See 273 for master reset version
prior to the LOW-to-HIGH clock transition for predictable
See 373 for transparent latch version
operation.
See 374 for 3-STATE version
ACT377 has TTL-compatible inputs
Ordering Information
Package
Order Number Number Package Description
74AC377SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74AC377SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC377MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
74ACT377SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ACT377SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT377MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
74ACT377PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
FACT is a trademark of Fairchild Semiconductor Corporation.
1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC377, 74ACT377 Rev. 1.6.174AC377, 74ACT377 Octal D-Type Flip-Flop with Clock Enable
Connection Diagram Pin Descriptions
Pin Names Description
D D Data Inputs
0 7
Clock Enable (Active LOW)
CE
Q Data Outputs
Q
0 7
CP Clock Pulse Input
Logic Symbols
IEEE/IEC
Mode Select-Function Table
Inputs Outputs
Operating Mode CP CE D Q
n n
Load 1' L H H
Load 0' L L L
Hold (Do Nothing) H X No Change
XHX No Change
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC377, 74ACT377 Rev. 1.6.1 2