DM74ALS374 Octal 3-STATE D-Type Edge-Triggered Flip-Flop September 1986 Revised February 2000 DM74ALS374 Octal 3-STATE D-Type Edge-Triggered Flip-Flop General Description Features This 8-bit register features totem-pole 3-STATE outputs Switching specifications at 50 pF designed specifically for driving highly-capacitive or rela- Switching specifications guaranteed over full tively low-impedance loads. The high-impedance state and temperature and V range CC increased high-logic-level drive provides this register with Advanced oxide-isolated, ion-implanted Schottky TTL the capability of being connected directly to and driving the process bus lines in a bus-organized system without need for inter- Functionally and pin-for-pin compatible with LS TTL face or pull-up components. It is particularly attractive for counterpart implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. Improved AC performance over DM74LS374 at approxi- mately half the power The eight flip-flops of the DM74ALS374 are edge-triggered D-type flip-flops. On the positive transition of the clock, the 3-STATE buffer-type outputs drive bus lines directly Q outputs will be set to the logic states that were set up at the D inputs. A buffered output control input can be used to place the eight outputs in either a normal logic state (HIGH or LOW logic levels) or a high-impedance state. In the high-imped- ance state the outputs neither load nor drive the bus lines significantly. The output control does not affect the internal operation of the flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are OFF. Ordering Code: Order Number Package Number Package Description DM74ALS374WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74ALS374SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74ALS374N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering code. Connection Diagram 2000 Fairchild Semiconductor Corporation DS006113 www.fairchildsemi.comFunction Table Output Output Clock D Control Q L HH L LL LL X Q 0 H XXZ L = LOW State H = HIGH State X = Dont Care = Positive Edge Transition Z = High Impedance State Q = Previous Condition of Q 0 Logic Diagram www.fairchildsemi.com 2 DM74ALS374