N74F273AN,602 NXP

INTEGRATED CIRCUITS 74F273A Octal D flip-flop Product specification 1996 Mar 12 IC15 Data Handbook Philips Semiconductors Product specification Octal D flipflop 74F273A All outputs will be forced Low independently of Clock or Data inputs FEATURES by a Low voltage level on the MR input. The device is useful for High impedance inputs for reduced loading applications where the true output only is required and the CP and (20A in Low and High states) MR are common to all elements. Ideal buffer for MOS microprocessor or memory Eight edgetriggered Dtype flipflops TYPICAL TYPICAL SUPPLY CURRENT TYPE f (TOTAL) MAX Buffered common clock 74F273A 170MHz 25mA Buffered asynchronous Master Reset See 74F377A for clock enable version See 74F373 for transparent latch version ORDERING INFORMATION See 74F374 for 3State version COMMERCIAL RANGE PACKAGES V = 5V10% PKG. DWG. CC T = 0C to +70C amb DESCRIPTION 20pin plastic DIP 74F273AN SOT146-1 The 74F273 has eight edgetriggered Dtype flipflops with individual D inputs and Q outputs. The common buffered Clock (CP) 20pin plastic SOL 74F273AD SOT163-1 and Master Reset (MR) inputs load and reset (clear) all flipflops simultaneously. The register is fully edgetriggered. The state of each D input, one setup time before the LowtoHigh clock transition, is transferred to the corresponding flipflops Q output. INPUT AND OUTPUT LOADING AND FAN-OUT TABLE 74F(U.L.) LOAD VALUE PINS DESCRIPTION HIGH/LOW HIGH/LOW D0 D7 Data inputs 1.0/0.033 20A/20A MR Master Reset input (activeLow) 1.0/0.033 20A/20A CP Clock pulse input (active rising edge) 1.0/0.033 20A/20A Q0 Q7 Data outputs 50/33 1.0mA/20mA PIN CONFIGURATION LOGIC SYMBOL MR 1 20 V CC 3 4 7 8 13 14 17 18 Q0 2 19 Q7 D0 3 18 D7 D0 D1 D2 D3 D4 D5 D6 D7 D1 4 17 D6 Q1 5 16 Q6 11 CP Q2 6 15 Q5 1 MR D2 7 14 D5 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 CP 2 5 6 9 12 15 16 19 SF00346 V = Pin 20 CC GND = Pin 10 SF00347 2 1996 Mar 12 8530066 16555