M74HCT273 OCTAL D TYPE FLIP FLOP WITH CLEAR HIGH SPEED : f = 80 MHz (TYP.) at V = 4.5V MAX CC LOW POWER DISSIPATION: I =4A(MAX.) at T =25C CC A COMPATIBLE WITH TTL OUTPUTS : V = 2V (MIN.) V = 0.8V (MAX) IH IL DIP SOP TSSOP SYMMETRICAL OUTPUT IMPEDANCE: I = I = 4mA (MIN) OH OL BALANCED PROPAGATION DELAYS: ORDER CODES t t PLH PHL PACKAGE TUBE T & R PIN AND FUNCTION COMPATIBLE WITH DIP M74HCT273B1R 74 SERIES 273 SOP M74HCT273M1R M74HCT273RM13TR TSSOP M74HCT273TTR DESCRIPTION The M74HCT273 is an high speed CMOS OCTAL When the CLEAR input is held low, the Q output D TYPE FLIP FLOP WITH CLEAR fabricated with are in the low logic level independent of the other 2 silicon gate C MOS technology. inputs. Information signals applied to D inputs are All inputs are equipped with protection circuits transferred to the Q outputs on the positive-going against static discharge and transient excess edge of the clock pulse. voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS August 2001 1/10 Obsolete Product(s) - Obsolete Product(s)M74HCT273 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION Master Reset Input 1 CLEAR (Active LOW) 2, 5, 6, 9, 12, Q0 to Q7 Flip Flop Outputs 15, 16, 19 3, 4, 7, 8, 13, D0 to D7 Data Inputs 14, 17, 18 Clock Input (LOW to 11 CLOCK HIGH, Edge Triggered) 10 GND Ground (0V) 20 Vcc Positive Supply Voltage TRUTH TABLE INPUTS OUTPUTS FUNCTION CLEAR CLOCK D Q L X X L CLEAR HLL HHH H X Qn NO CHANGE X : Dont Care LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/10 Obsolete Product(s) - Obsolete Product(s)