M74HCT174 HEX D-TYPE FLIP FLOP WITH CLEAR HIGH SPEED : f = 56MHz (TYP.) at V = 4.5V MAX CC LOW POWER DISSIPATION: I =4A(MAX.) at T =25C CC A COMPATIBLE WITH TTL OUTPUTS : V = 2V (MIN.) V = 0.8V (MAX) IH IL DIP SOP TSSOP SYMMETRICAL OUTPUT IMPEDANCE: I = I = 4mA (MIN) OH OL BALANCED PROPAGATION DELAYS: ORDER CODES t t PLH PHL PACKAGE TUBE T & R PIN AND FUNCTION COMPATIBLE WITH DIP M74HCT174B1R 74 SERIES 174 SOP M74HCT174M1R M74HCT174RM13TR TSSOP M74HCT174TTR DESCRIPTION The M74HCT174 is an high speed CMOS HEX D-TYPE FLIP FLOP WITH CLEAR fabricated with (CLR) input is held low, the Q outputs are held low 2 silicon gate C MOS technology. independently of the other inputs. Information signals applied to D inputs are All inputs are equipped with protection circuits transferred to the Q output on the positive going against static discharge and transient excess edge of the CLOCK (CK) pulse. When the CLEAR voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS August 2001 1/10 Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) M74HCT174 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION Asynchronous Master 1 CLEAR Reset (Active Low) 2, 5, 7, 10, Q0 to Q5 Flip-Flop Outputs 12, 15 3, 4, 6, 11, D0 to D5 Data Inputs 13, 14 Clock Input (LOW to 9 CLOCK HIGH, edge triggered) 8 GND Ground (0V) 16 Vcc Positive Supply Voltage TRUTH TABLE INPUTS OUTPUTS FUNCTION CLEAR DCK Q L X X L CLEAR HL L HH H H X Qn NO CHANGE X : Dont Care LOGIC DIAGRAM This logic diagram has not to be used to estimate propagation delays 2/10 Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s)