M74HC74 DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR HIGH SPEED : f = 67MHz (TYP.) at V = 6V MAX CC LOW POWER DISSIPATION: I =2A(MAX.) at T =25C CC A HIGH NOISE IMMUNITY: V = V = 28 % V (MIN.) NIH NIL CC DIP SOP TSSOP SYMMETRICAL OUTPUT IMPEDANCE: I = I = 4mA (MIN) OH OL BALANCED PROPAGATION DELAYS: t t PLH PHL ORDER CODES WIDE OPERATING VOLTAGE RANGE: PACKAGE TUBE T & R V (OPR) = 2V to 6V CC DIP M74HC74B1R PIN AND FUNCTION COMPATIBLE WITH SOP M74HC74M1R M74HC74RM13TR 74 SERIES 74 TSSOP M74HC74TTR DESCRIPTION The M74HC74 is an high speed CMOS DUAL D independent of the clock and accomplished by a TYPE FLIP FLOP WITH CLEAR fabricated with low on the appropriate input. 2 silicon gate C MOS technology. All inputs are equipped with protection circuits A signal on the D INPUT is transferred on the Q against static discharge and transient excess OUTPUT during the positive going transition of the voltage. clock pulse. CLEAR and PRESET are PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/12M74HC74 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION Asynchronous Reset - 1,13 1CLR, 2CLR Direct Input 2, 12 1D, 2D Data Inputs Clock Input 3, 11 1CK, 2CK (LOW-to-HIGH, Edge-Triggered) Asynchronous Set - Direct 4, 10 1PR, 2PR Input 5, 9 1Q, 2Q True Flip-Flop Outputs Complement Flip-Flop 6, 8 1Q, 2Q Outputs 7 GND Ground (0V) 14 Vcc Positive Supply Voltage TRUTH TABLE INPUTS OUTPUTS FUNCTION CLR PR DCK Q Q L H X X L H CLEAR H L X X H L PRESET L L X X H H ---- H H L L H ---- H H H H L ---- Q Q HH X NO CHANGE n n X : Dont Care LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/12