M74HCT138 3 TO 8 LINE DECODER (INVERTING) HIGH SPEED: t = 16ns (TYP.) at V = 4.5V PD CC LOW POWER DISSIPATION: I = 4A(MAX.) at T =25C CC A COMPATIBLE WITH TTL OUTPUTS : V = 2V (MIN.) V = 0.8V (MAX) IH IL DIP SOP TSSOP SYMMETRICAL OUTPUT IMPEDANCE: I = I = 4mA (MIN) OH OL BALANCED PROPAGATION DELAYS: t t ORDER CODES PLH PHL PIN AND FUNCTION COMPATIBLE WITH PACKAGE TUBE T & R 74 SERIES 138 DIP M74HCT138B1R SOP M74HCT138M1R M74HCT138RM13TR DESCRIPTION TSSOP M74HCT138TTR The M74HCT138 is an high speed CMOS 3 TO 8 LINE DECODER fabricated with silicon gate 2 C MOS technology. enable inputs are provided to ease cascade If the device is enabled, 3 binary select inputs (A, connection and application of address decoders B, and C) determine which one of the outputs will for memory systems. go low. If enable input G1 is held low or either G2A All inputs are equipped with protection circuits or G2B is held high, the decoding function is against static discharge and transient excess inhibited and all the 8 outputs go high. Three voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS August 2001 1/9 Obsolete Product(s) - Obsolete Product(s)M74HCT138 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1, 2, 3 A, B, C Address Inputs 4, 5 G2A, G2B Enable Inputs 6 G1 Enable Input 9, 10, 11, 12, Y0 to Y7 Data Outputs 13, 14, 15, 7 8 GND Ground (0V) 16 V Positive Supply Voltage CC TRUTH TABLE INPUTS OUTPUTS ENABLE SELECT G2B G2A G1 CBA Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X L X X X HHHHH HHH XH XXXX HHHHH HHH HXXXXX HHHHH HHH LL H LLLL HHHH HHH L LHL LH HLH H H H H H L LHLHLH HLH H H H H L L H L HHHHH L H HHH L L HH L L HHHH L HHH L L HH L HHHHHH L H H L L HHH L HHHHH H L H L L HHHHHHHHH HH L X : Dont Care LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/9 Obsolete Product(s) - Obsolete Product(s)