M74HCT164 8 BIT SIPO SHIFT REGISTER HIGH SPEED: t = 24 ns (TYP.) at V = 4.5V PD CC LOW POWER DISSIPATION: I = 4A(MAX.) at T =25C CC A COMPATIBLE WITH TTL OUTPUTS : V = 2V (MIN.) V = 0.8V (MAX) IH IL DIP SOP TSSOP BALANCED PROPAGATION DELAYS: t t PLH PHL SYMMETRICAL OUTPUT IMPEDANCE: I = I = 4mA (MIN) ORDER CODES OH OL PIN AND FUNCTION COMPATIBLE WITH PACKAGE TUBE T & R 74 SERIES 164 DIP M74HCT164B1R SOP M74HCT164M1R M74HCT164RM13TR DESCRIPTION TSSOP M74HCT164TTR The M74HCT164 is an high speed CMOS 8 BIT SIPO SHIFT REGISTER fabricated with silicon 2 gate C MOS technology. the two data inputs (A x B), the data that existed The 74HCT164 is an 8 bit shift register with serial before the rising clock edge. A low level on the data entry and an output from each of the eight clear input overrides all other inputs and clears the register asynchronously, forcing all Q outputs low. stages. Data is entered serially through one of two inputs (A or B), either of these inputs can be used The M74HCT164 is designed to directly interface 2 as an active high enable for data entry through the HSCMOS systems with TTL and NMOS other input. An unused input must be high, or both components. inputs connected together. Each low-to-high All inputs are equipped with protection circuits transition on the clock inputs shifts data one place against static discharge and transient excess to the right and enters into QA, the logic NAND of voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/11 Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) M74HCT164 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1,2 A, B Data Inputs 3, 4, 5, 6, 10, QA to QH Outputs 11, 12, 13 Clock Input (LOW to 8 CLOCK HIGH, Edge Triggered 9 CLEAR Master Reset Input 7 GND Ground (0V) 14 Vcc Positive Supply Voltage TRUTH TABLE INPUTS OUTPUTS SERIAL IN CLEAR CLOCK QA QB ........... QH AB L X X X L L ........... L H X X NO CHANGE H L X L QAn ........... QGn H X L L QAn ........... QGn H H H H QAn ........... QGn X : Dont Care QAn - QGn : The level of QA - QG, respectively. before the most-recent transition of the clock LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/11 Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s)