M74HC4040RM13TR STMicroelectronics

M74HC4040 12 STAGE BINARY COUNTER HIGH SPEED : f = 70 MHz (TYP.) at V = 6V MAX CC LOW POWER DISSIPATION: I =4A(MAX.) at T =25C CC A HIGH NOISE IMMUNITY: V = V = 28 % V (MIN.) NIH NIL CC DIP SOP TSSOP SYMMETRICAL OUTPUT IMPEDANCE: I = I = 4mA (MIN) OH OL BALANCED PROPAGATION DELAYS: ORDER CODES t t PLH PHL PACKAGE TUBE T & R WIDE OPERATING VOLTAGE RANGE: V (OPR) = 2V to 6V DIP M74HC4040B1R CC PIN AND FUNCTION COMPATIBLE WITH SOP M74HC4040M1R M74HC4040RM13TR 74 SERIES 4040 TSSOP M74HC4040TTR DESCRIPTION transition on the CLOCK input increments the The M74HC4040 is an high speed CMOS 12 counter by one. STAGE BINARY COUNTER fabricated with For M74HC4040 each division stage has an 2 silicon gate C MOS technology. output the final frequency is 1/4096 f . IN A clear input is used to reset the counter to the all All inputs are equipped with protection circuits low level state. A high level on CLEAR against static discharge and transient excess accomplishes the reset function. A negative voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/11 Obsolete Product(s) - Obsolete Product(s)M74HC4040 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 9, 7, 6, 5, 3, 2, 4, 13, 12, Q1 to Q12 Parallel Outputs 14, 15, 1 Clock Input (LOW to 10 CLOCK HIGH, Edge Triggered) 11 CLEAR Reset Inputs 8 GND Ground (0V) 16 Vcc Positive Supply Voltage TRUTH TABLE CLOCK CLEAR OUTPUT STATE X H ALL OUTPUTS = L NO CHANGE L ADVANCE TO NEXT STATE LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/11 Obsolete Product(s) - Obsolete Product(s)