M74HC165TTR STMicroelectronics

M74HC165 8-bit PISO shift register Features High speed: t = 15 ns (typ.) at V = 6 V PD CC SO-16 Low power dissipation: DIP-16 I = 4 A (max.) at T = 25 C CC A High noise immunity: V = V = 28 % V (Min.) NIH NIL CC Symmetrical output impedance: TSSOP16 I = I = 4 mA (min) OH OL Balanced propagation delays: t t PLH PHL Description Wide operating voltage range: The M74HC165 is a high speed CMOS 8-bit V (opr) = 2 V to 6 V CC PISO (parallel-in-serial-out) shift register Pin and function compatible with 2 fabricated with silicon gate C MOS technology. 74 series 165 This device contains eight clocked master slave RS flip-flops connected as a shift register, with auxiliary gating to provide overriding asynchronous parallel entry. The parallel data enter when the shift/load input is low and can change while shift/load is low, provided that the recommended set-up and hold times are observed. For clocked operation, shift/load must be high. The two clock inputs perform identically: one can be used as a clock inhibit by applying a high signal, to allow this operation clocking is accomplished through a 2-input nor gate. To avoid double clocking, however, the inhibit signal should only go high while the clock is high. Otherwise the rising inhibit signal causes the same response as rising clock edge. All inputs are equipped with protection circuits against static discharge and transient excess voltage. Table 1. Device summary Order code Package Packaging M74HC165B1R DIP-16 Tube M74HC165RM13TR SO-16 Tape and reel M74HC165TTR TSSOP16 Tape and reel May 2008 Rev 5 1/21 www.st.com 21Contents M74HC165 Contents 1 Logic symbols and I/O equivalent circuit 3 2 Pin settings 4 2.1 Pin connection 4 2.2 Pin description 4 3 Logic states 5 3.1 Truth table 5 3.2 Logic diagram . 5 3.3 Timing chart 6 4 Maximum rating . 7 4.1 Recommended operating conditions . 7 5 Electrical characteristics . 8 6 Test circuit 11 7 Waveforms 12 8 Package mechanical data 14 9 Revision history . 17 2/21