74AC161 74ACT161 Synchronous Presettable Binary Counter November 1988 Revised September 2003 74AC161 74ACT161 Synchronous Presettable Binary Counter General Description Features The AC/ACT161 are high-speed synchronous modulo-16 I reduced by 50% CC binary counters. They are synchronously presettable for Synchronous counting and loading application in programmable dividers and have two types High-speed synchronous expansion of Count Enable inputs plus a Terminal Count output for Typical count rate of 125 MHz versatility in forming synchronous multistage counters. The AC/ACT161 has an asynchronous Master Reset input that Outputs source/sink 24 mA overrides all other inputs and forces the outputs LOW. ACT161 has TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74AC161SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74AC161SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC161MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC161PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74ACT161SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74ACT161SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT161MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT161PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering code. Connection Diagram Logic Symbols IEEE/IEC Pin Descriptions Pin Names Description CEP Count Enable Parallel Input CET Count Enable Trickle Input CP Clock Pulse Input MR Asynchronous Master Reset Input P P Parallel Data Inputs 0 3 PE Parallel Enable Inputs Q Q Flip-Flop Outputs 0 3 TC Terminal Count Output FACT is a trademark of Fairchild Semiconductor Corporation. 2003 Fairchild Semiconductor Corporation DS009931 www.fairchildsemi.comits the clock period is the CP to TC delay of the first stage Functional Description plus the CEP to CP setup time of the last stage. The TC The AC/ACT161 count in modulo-16 binary sequence. output is subject to decoding spikes due to internal race From state 15 (HHHH) they increment to state 0 (LLLL). conditions and is therefore not recommended for use as a The clock inputs of all flip-flops are driven in parallel clock or asynchronous reset for flip-flops, registers or through a clock buffer. Thus all changes of the Q outputs counters. (except due to Master Reset of the AC/ACT161) occur as a Logic Equations: Count Enable = CEP CET PE result of, and synchronous with, the LOW-to-HIGH transi- TC = Q Q Q Q CET tion of the CP input signal. The circuits have four funda- 0 1 2 3 mental modes of operation, in order of precedence: asynchronous reset, parallel load, count-up and hold. Five Mode Select Table control inputsMaster Reset, Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET) Action on the Rising determine the mode of operation, as shown in the Mode PE CET CEP Clock Edge ( ) Select Table. A LOW signal on MR overrides all other X X X Reset (Clear) inputs and asynchronously forces all outputs LOW. A LOW signal on PE overrides counting and allows information on L X X Load (P Q ) n n the Parallel Data (P ) inputs to be loaded into the flip-flops n H H H Count (Increment) on the next rising edge of CP. With PE and MR HIGH, CEP H L X No Change (Hold) and CET permit counting when both are HIGH. Conversely, H X L No Change (Hold) a LOW signal on either CEP or CET inhibits counting. H = HIGH Voltage Level The AC/ACT161 use D-type edge-triggered flip-flops and L = LOW Voltage Level changing the PE, CEP, and CET inputs when the CP is in X = Immaterial either state does not cause errors, provided that the recom- mended setup and hold times, with respect to the rising State Diagram edge of CP, are observed. The Terminal Count (TC) output is HIGH when CET is HIGH and counter is in state 15. To implement synchro- nous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Figure 1 shows the connections for simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min in the Up mode, or min to max in the Down mode, to start its final cycle. Since this final cycle requires 16 clocks to com- plete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that lim- FIGURE 1. Multistage Counter with Ripple Carry FIGURE 2. Multistage Counter with Lookahead Carry www.fairchildsemi.com 2 74AC161 74ACT161