74AC163 74ACT163 Synchronous Presettable Binary Counter
November 1988
Revised February 2000
74AC163 74ACT163
Synchronous Presettable Binary Counter
General Description Features
The AC/ACT163 are high-speed synchronous modulo-16 I reduced by 50%
CC
binary counters. They are synchronously presettable for
Synchronous counting and loading
application in programmable dividers and have two types
High-speed synchronous expansion
of Count Enable inputs plus a Terminal Count output for
Typical count rate of 125 MHz
versatility in forming synchronous multistage counters. The
AC/ACT163 has a Synchronous Reset input that overrides
Outputs source/sink 24 mA
counting and parallel loading and allows the outputs to be
ACT163 has TTL-compatible inputs
simultaneously reset on the rising edge of the clock.
Ordering Code:
Order Number Package Number Package Description
74AC163SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Body
74AC163SJ M16D 16-Lead Small Outline Package, (SOP), EIAJ TYPE II, 5.3mm Wide
74AC163MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC163PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACT163SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Body
74ACT163SJ M16D 16-Lead Small Outline Package, (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT163MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT163PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering code.
Connection Diagram Pin Descriptions
Pin Names Description
CEP Count Enable Parallel Input
CET Count Enable Trickle Input
CP Clock Pulse Input
SR Synchronous Reset Input
P P Parallel Data Inputs
0 3
PE Parallel Enable Input
Q Q Flip-Flop Outputs
0 3
TC Terminal Count Output
2000 Fairchild Semiconductor Corporation DS009932 www.fairchildsemi.comLogic Symbols Functional Description
The AC/ACT163 counts in modulo-16 binary sequence.
From state 15 (HHHH) it increments to state 0 (LLLL). The
clock inputs of all flip-flops are driven in parallel through a
clock buffer. Thus all changes of the Q outputs occur as a
result of, and synchronous with, the LOW-to-HIGH transi-
tion of the CP input signal. The circuits have four funda-
mental modes of operation, in order of precedence:
synchronous reset, parallel load, count-up and hold. Four
control inputsSynchronous Reset (SR), Parallel Enable
(PE), Count Enable Parallel (CEP) and Count Enable
Trickle (CET)determine the mode of operation, as shown
IEEE/IEC in the Mode Select Table. A LOW signal on SR overrides
counting and parallel loading and allows all outputs to go
LOW on the next rising edge of CP. A LOW signal on PE
overrides counting and allows information on the Parallel
Data (P ) inputs to be loaded into the flip-flops on the next
n
rising edge of CP. With PE and SR HIGH, CEP and CET
permit counting when both are HIGH. Conversely, a LOW
signal on either CEP or CET inhibits counting.
The AC/ACT163 uses D-type edge-triggered flip-flops and
changing the SR, PE, CEP and CET inputs when the CP is
in either state does not cause errors, provided that the rec-
ommended setup and hold times, with respect to the rising
edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and counter is in state 15. To implement synchro-
nous multistage counters, the TC outputs can be used with
the CEP and CET inputs in two different ways.
Mode Select Table
Figure 1 shows the connections for simple ripple carry, in
which the clock period must be longer than the CP to TC
SR PE CET CEP Action on the Rising
delay of the first stage, plus the cumulative CET to TC
Clock Edge ( ) delays of the intermediate stages, plus the CET to CP
setup time of the last stage. This total delay plus setup time
L X X X Reset (Clear)
sets the upper limit on clock frequency. For faster clock
rates, the carry lookahead connections shown in Figure 2
H L X X Load (P Q )
n n
are recommended. In this scheme the ripple delay through
H H H H Count (Increment)
the intermediate stages commences with the same clock
that causes the first stage to tick over from max to min in
H H L X No Change (Hold)
the Up mode, or min to max in the Down mode, to start its
H H X L No Change (Hold)
final cycle. Since this final cycle takes 16 clocks to com-
H = HIGH Voltage Level
plete, there is plenty of time for the ripple to progress
L = LOW Voltage Level
through the intermediate stages. The critical timing that lim-
X = Immaterial
its the clock period is the CP to TC delay of the first stage
plus the CEP to CP setup time of the last stage. The TC
output is subject to decoding spikes due to internal race
conditions and is therefore not recommended for use as a
clock or asynchronous reset for flip-flops, registers or
counters.
Logic Equations: Count Enable = CEP CET PE
TC = Q Q Q Q CET
0 1 2 3
www.fairchildsemi.com 2
74AC163 74ACT163