M74HC390B1R STMicroelectronics

M74HC390 Dual decade counter Features HIgh Speed: f = 79MHz (Typ.) at V = 6V MAX CC Low power dissipation: I = 4A (Max.) at T = 25C CC A High noise immunity: V = V = 28 % V (Min.) NIH NIL CC DIP-16 SO-16 Balanced propagation delays: t t PLH PHL Wide operating voltage range: V (Opr) = 2V to 6V CC Pin and function compatible with 74 series 390 Description Each 4-bit counter is increased on the high to low The M74HC390 is an high speed CMOS dual transition (negative edge) of the clock input, and decade counter fabricated with silicon gate each has an independent clear input. When clear C2MOS technology. is set low all four bits of each counter are set to This dual decade counter contains two low. This enables count truncation and allows the independent ripple carry counters. Each counter implementation of divide by N counter is composed of a divide by two and divide by five configuration. counter. The divide by two and divide by five All inputs are equipped with protection circuits counters can be cascaded to form dual decade, against static discharge and transient excess dual biquinary, or various combination up to a voltage. single divide by 100 counter. Order codes Part number Package Packaging M74HC390B1R DIP-14 Tube M74HC390RM13TR SO-14 Tape and reel July 2006 Rev 2 1/17 www.st.com 17 Obsolete Product(s) - Obsolete Product(s)Contents M74HC390 Contents 1 Pin settings 3 1.1 Pin connection 3 1.2 Pin description 3 2 Device summary 4 3 Truth table . 5 4 Block and logic diagrams . 6 5 Timing chart 7 6 Maximum rating . 8 6.1 Recommended operating conditions . 8 7 Electrical characteristics . 9 8 Test circuit 12 9 Waveforms 12 10 Package mechanical data 13 11 Revision history . 16 2/17 Obsolete Product(s) - Obsolete Product(s)