M74HC4017
DECADE COUNTER/DIVIDER
HIGH SPEED :
t = 21 ns (TYP.) at V = 6V
PD CC
LOW POWER DISSIPATION:
I =4A(MAX.) at T =25C
CC A
HIGH NOISE IMMUNITY:
V = V = 28 % V (MIN.)
NIH NIL CC
DIP SOP TSSOP
SYMMETRICAL OUTPUT IMPEDANCE:
|I | = I = 4mA (MIN)
OH OL
BALANCED PROPAGATION DELAYS:
t t
PLH PHL ORDER CODES
WIDE OPERATING VOLTAGE RANGE:
PACKAGE TUBE T & R
V (OPR) = 2V to 6V
CC
DIP M74HC4017B1R
PIN AND FUNCTION COMPATIBLE WITH
SOP M74HC4017M1R M74HC4017RM13TR
74 SERIES 4017
TSSOP M74HC4017TTR
DESCRIPTION
The M74HC4017 is an high speed CMOS
be used in conjunction with the CLOCK ENABLE
DECADE COUNTER/DIVIDER fabricated with
(CKEN)to cascade several stages.
2
silicon gate C MOS technology.
The CLOCK ENABLE input disables counting
The M74HC4017 is a 5-stage Johnson counter
when in the high state. A CLEAR (CLR) input is
with 10 decoded outputs. Each of the decoded
also provided which when taken high sets all the
outputs is normally low and sequentially goes high
decoded outputs low.
on the low to high transition of the clock input.
All inputs are equipped with protection circuits
Each output stays high for one clock period of the
against static discharge and transient excess
10 clock period cycle. The CARRY output goes
voltage.
low to high after OUTPUT 10 goes low, and can
PIN CONNECTION AND IEC LOGIC SYMBOLS
August 2001 1/12
Obsolete Product(s) - Obsolete Product(s)M74HC4017
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION
3, 2, 4, 7, 10,
Q0 to Q9 Decoded Outputs
1, 5, 6, 9, 11
Carry Output
C
12
OUT
(Active LOW)
Clock Enable Input
13 CKEN
(Active LOW)
Clock Input (LOW to
14 CLOCK
HIGH, Edge Triggered)
Master Reset Inputs
15 CLEAR
(Active HIGH)
8 GND Ground (0V)
16 Vcc Positive Supply Voltage
TRUTH TABLE
CLOCK CLOCK ENABLE CLEAR DECODED OUTPUT(H)
XX H QO
LXL Qn
XH L Qn
L L Qn + 1
LL Qn
HLQn
H L Qn + 1
X : Dont Care
Qn : No Change
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
2/12
Obsolete Product(s) - Obsolete Product(s)