MC10E137, MC100E137
5 VECL 8Bit Ripple Counter
Description
The MC10E/100E137 is a very high speed binary ripple counter. The
two least significant bits were designed with very fast edge rates while
the more significant bits maintain standard ECLinPS output edge
rates. This allows the counter to operate at very high frequencies while
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maintaining a moderate power dissipation level.
The device is ideally suited for multiple frequency clock generation
as well as a counter in a high performance ATE time measurement
board.
Both asynchronous and synchronous enables are available to
maximize the devices flexibility for various applications. The
PLCC28
asynchronous enable input, A_Start, when asserted enables the counter
FN SUFFIX
while overriding any synchronous enable signals. The E137 features
CASE 77602
XORed enable inputs, EN1 and EN2, which are synchronous to the
MARKING DIAGRAM*
CLK input. When only one synchronous enable is asserted the counter
becomes disabled on the next CLK transition; all outputs remain in the
1
previous state poised for the other synchronous enable or A_Start to be
asserted to re-enable the counter. Asserting both synchronous enables
causes the counter to become enabled on the next transition of the CLK.
MCxxxE137FNG
If EN1 (or EN2) and CLK edges are coincident, sufficient delay has
AWLYYWW
been inserted in the CLK path (to compensate for the XOR gate delay
and the internal D-flip flop setup time) to insure that the synchronous
enable signal is clocked correctly, hence, the counter is disabled.
All input pins left open will be pulled LOW via an input pulldown
xxx = 10 or 100
resistor. Therefore, do not leave the differential CLK inputs open. A = Assembly Location
WL = Wafer Lot
Doing so causes the current source transistor of the input clock gate to
YY = Year
become saturated, thus upsetting the internal bias regulators and
WW = Work Week
jeopardizing the stability of the device.
G = Pb-Free Package
The asynchronous Master Reset resets the counter to an all zero state
*For additional marking information, refer to
upon assertion.
Application Note AND8002/D.
The V pin, an internally generated voltage supply, is available to
BB
this device only. For single-ended input conditions, the unused
ORDERING INFORMATION
differential input is connected to V as a switching reference voltage.
BB
V may also rebias AC coupled inputs. When used, decouple V and
BB BB
Device Package Shipping
V via a 0.01F capacitor and limit current sourcing or sinking to
CC
MC10E137FNG PLCC28 37 Units/Tube
0.5 mA. When not used, V should be left open.
BB
(Pb-Free)
The 100 Series contains temperature compensation.
MC100E137FNG PLCC28 37 Units/Tube
Features (Pb-Free)
Differential Clock Input and Data Output Pins
Human Body Model: > 2 kV
V Output for Single-Ended Use
BB
Machine Model: > 200 V
Synchronous and Asynchronous Enable Pins
Meets or Exceeds JEDEC Spec EIA/JESD78 IC
Asynchronous Master Reset
Latchup Test
PECL Mode Operating Range:
Moisture Sensitivity Level: 3 (Pb-Free)
V = 4.2 V to 5.7 V with V = 0 V
CC EE
For Additional Information, see Application Note
NECL Mode Operating Range:
AND8003/D
V = 0 V with V = 4.2 V to 5.7 V
CC EE
Flammability Rating: UL 94 V0 @ 0.125 in,
Internal Input 50 k Pull-down Resistors
Oxygen Index: 28 to 34
Transistor Count = 330 devices
These Devices are Pb-Free, Halogen Free and are
ESD Protection:
RoHS Compliant
Semiconductor Components Industries, LLC, 2016
1 Publication Order Number:
July, 2016 Rev. 9 MC10E137/DMC10E137, MC100E137
Q7 Q7 Q6 Q6 V Q5 Q5
CCO
Table 1. PIN DESCRIPTION
25 24 23 22 21 20 19
PIN FUNCTION
18
A_Start 26 Q4
CLK, CLK ECL Differential Clock Inputs
17
EN1 27 Q4
Q0-Q7, Q0-Q7 ECL Differential Q Outputs
16
EN2 28 V
CC A_Start ECL Asynchronous Enable Input
Pinout: 28-Lead PLCC
EN1, EN2 ECL Synchronous Enable Inputs
V 1 15 Q3
EE (Top View)
MR Asynchronous Master Reset
V Reference Voltage Output
CLK 2 14 Q3
BB
V , V Positive Supply
CC CCO
CLK 3
13 Q2
V Negative Supply
EE
12
V 4 Q2
BB
5 6 7
8 9 10 11
MR V Q0 Q0 Q1 Q1 V
CCO CCO
* All V and V pins are tied together on the die.
CC CCO
Warning: All V , V , and V pins must be externally
CC CCO EE
connected to Power Supply to guarantee proper operation.
Figure 1. 28-Lead Pinout
A_Start
EN1
R
Q0 Q0 Q1 Q1 Q7 Q7
D
EN2
Q
CLK
Q
CLK
CLK Q CLK Q CLK Q
CLK CLK Q CLK Q CLK Q
CLK
D D D
R R R
V
BB
MR
Figure 2. Logic Diagram
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2