MC100E310 5 V ECL Low Voltage 2:8 Differential Fanout Buffer Description The MC100E310 is a low voltage, low skew 2:8 differential ECL fanout buffer designed with clock distribution in mind. The device www.onsemi.com features fully differential clock paths to minimize both device and system skew. The E310 offers two selectable clock inputs to allow for redundant or test clocks to be incorporated into the system clock trees. The lowest TPD delay time results from terminating only one output pair, and the greatest TPD delay time results from terminating all the output pairs. This shift is about 1020 pS in TPD. The skew between any two output pairs within a device is typically about 25 nS. If other output pairs are not terminated, the lowest TPD delay time results PLCC28 from both output pairs and the skew is typically 25 nS. When all FN SUFFIX CASE 77602 outputs are terminated, the greatest TPD (delay time) occurs and all outputs display about the same 1020 ps increase in TPD, so the relative skew between any two output pairs remains about 25 ns. For more information on using PECL, designers should refer to MARKING DIAGRAM* ON Semiconductor Application Note AN1406/D. The V pin, an internally generated voltage supply, is available to BB 128 this device only. For single-ended input conditions, the unused differential input is connected to V as a switching reference voltage. BB V may also rebias AC coupled inputs. When used, decouple V BB BB MC100E310FNG and V via a 0.01 F capacitor and limit current sourcing or sinking CC AWLYYWW to 0.5 mA. When not used, V should be left open. BB The 100 Series Contains Temperature Compensation. Features A = Assembly Location Dual Differential Fanout Buffers WL = Wafer Lot 200 ps Part-to-Part Skew YY = Year 50 ps Output-to-Output Skew WW = Work Week G = Pb-Free Package 28-lead PLCC Packaging *For additional marking information, refer to Q Output will Default LOW with Inputs Open or at V EE Application Note AND8002/D. PECL Mode Operating Range: V = 4.2 V to 5.7 V CC with V = 0 V EE NECL Mode Operating Range: V = 0 V CC ORDERING INFORMATION with V = 4.2 V to 5.7 V EE Device Package Shipping Internal Input 50 k Pulldown Resistors MC100E310FNG PLCC28 37 Units / Tube ESD Protection: (Pb-Free) > 2 kV Human Body Model MC100E310FNR2G PLCC28 500 Tape & Reel > 200 V Machine Model (Pb-Free) Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test For information on tape and reel specifications, in- Moisture Sensitivity: Level 3 (Pb-Free) cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications (For Additional Information, see Application Note AND8003/D) Brochure, BRD8011/D. Flammability Rating: UL 94 V0 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 212 Devices These Devices are Pb-Free, Halogen Free and are RoHS Compliant Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 7 MC100E310/DMC100E310 Q0 Q0 Q0 Q1 V Q1 Q2 Q2 CCO Q0 25 24 23 22 21 20 19 Q1 V 26 18 Q3 EE Q1 Q2 27 17 Q3 CLK SEL Q2 Q4 CLKa 28 16 CLKa Q3 CLKa Pinout: 28-Lead PLCC Q3 V 15 V CC 1 CCO (Top View) CLKb Q4 CLKa 2 14 Q4 CLKb Q4 3 13 Q5 V BB Q5 CLK SEL Q5 CLKb 4 12 Q5 5 6 789 10 11 Q6 Q6 CLKb NC Q7 V Q7 Q6 Q6 CCO Q7 * All V and V pins are tied together on the die. CC CCO Q7 Warning: All V , V , and V pins must be externally CC CCO EE V BB connected to Power Supply to guarantee proper operation. Figure 1. Logic Diagram and Pinout Assignment Figure 2. Logic Symbol Table 1. PIN DESCRIPTION Table 2. FUNCTION TABLE PIN Function PIN Function CLKa, CLKb ECL Differential Input Pairs 0 CLKa Selected CLKa, CLKb ECL Differential Input Pairs 1 CLKb Selected Q0:7 Q0:7 ECL Differential Outputs CLK SEL ECL Input Clock Select V Reference Voltage Output BB V V Positive Supply CC, CCO V Negative Supply EE NC No Connect www.onsemi.com 2