MC10H645FNG ON Semiconductor

MC10H645 2:1:9 TTL Clock Driver Description The MC10H645 is a single supply, low skew, TTL I/O 2:1:9 Clock Driver. Devices in the H600 clock driver family utilizes the PLCC28 for optimal power and signal pin placement. The device features a 24 mA TTL output stage with AC www.onsemi.com performance specified into a 50 pF load capacitance. A 2:1 input Mux is provided on chip to allow for distributing both system and diagnostic clock signals or designing clock redundancy into a system. With the SEL input held LOW the DO input will be selected, while the D1 input is selected when the SEL input is forced HIGH. Features PLCC Low Skew Typically 0.65 ns Within Device FN SUFFIX CASE 776 Guaranteed Skew Spec 1.25 ns ParttoPart Input Clock Muxing MARKING DIAGRAM Differential ECL Internal Design Single Supply Extra TTL and ECL Power/Ground Pins These Devices are PbFree and are RoHS Compliant* MC10H645G AWLYYWW A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = PbFree Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: April, 2015 Rev. 7 MC10H645/DMC10H645 TTL Outputs GT Q6 VT Q7 VT Q8 GT Q0 25 24 23 22 21 20 19 TTL Inputs GT 26 18 NC MUX Q1 Q5 27 17 D0 D0 D0 Q2 D0 Q VT 28 16 D1 Q D1 D1 Q3 Q4 15 VE 1 D1 Q4 VT 2 14 SEL S S Q3 3 13 GE Q5 SEL GT 4 12 NC Q6 56 7 8 9 10 11 Q7 GT Q2 VT Q1 VT Q0 GT Q8 Figure 2. Pinout: 28Lead PLCC Figure 1. Logic Diagram (Top View) Table 1. PIN NAMES PIN FUNCTION GT TTL Ground (0 V) VT TTL V (+5.0 V) CC VE ECL V (+5.0 V) CC GE ECL Ground (0 V) Dn TTL Signal Input Q0 Q8 TTL Signal Outputs SEL TTL Mux Select Table 2. PIN DESCRIPTIONS Pin Symbol Description Pin Symbol Description 1 Q4 Signal Output (TTL) 15 VE ECL V (+5.0 V) CC 2 VT TTL V (+5.0 V) 16 D1 Signal Input (TTL) CC 3 Q3 Signal Output (TTL) 17 D0 Signal Input (TTL) 4 GT TTL Ground (0 V) 18 NC No Connection 5 GT TTL Ground (0 V) 19 GT TTL Ground (0 V) 6 Q2 Signal Output (TTL) 20 Q8 Signal Output (TTL) 7 VT TTL V (+5.0 V) 21 VT TTL V (+5.0 V) CC CC 8 Q1 Signal Output (TTL) 22 Q7 Signal Output (TTL) 9 VT TTL V (+5.0 V) 23 VT TTL V (+5.0 V) CC CC 10 Q0 Signal Output (TTL) 24 Q6 Signal Output (TTL) 11 GT TTL Ground (0 V) 25 GT TTL Ground (0 V) 12 NC No Connection 26 GT TTL Ground (0 V) 13 GE ECL Ground 27 Q5 Signal Output (TTL) 14 SEL Select Input (TTL) 28 VT TTL V (+5.0 V) CC Table 3. TRUTH TABLE D0 D1 SEL Q L X L L H X L H X L H L X H H H www.onsemi.com 2