12:1, Differential-to-3.3V, 2.5V ICS853S012I Datasheet LVPECL Clock/Data Multiplexer Description Features The ICS853S012I is an 12:1 Differential-to-3.3V or 2.5V LVPECL High speed 12:1 differential multiplexer Clock/Data Multiplexer which can operate up to 3.2GHz. The One differential 3.3V or 2.5V LVPECL output ICS853S012I has twelve differential selectable clock inputs. The Twelve selectable differential clock or data inputs CLK, nCLK input pairs can accept LVPECL, LVDS or CML levels. CLKx, nCLKx pairs can accept the following differential input The fully differential architecture and low propagation delay make levels: LVPECL, LVDS, CML the device ideal for use in clock distribution circuits. The select Maximum output frequency: 3.2GHz pins have internal pull-down resistors. Translates any single ended input signal to LVPECL levels with resistor bias on nCLKx input Additive phase jitter, RMS: 0.144ps (typical) Part-to-part skew: 250ps (maximum) Propagation delay: 1.15ns (maximum) Full 3.3V or 2.5V operating supply modes -40C to 85C ambient operating temperature Available lead-free (RoHS 6) package Block Diagram Pin Assignment Pulldown CLK0 Pullup/Pulldown nCLK0 Pulldown CLK1 32 31 30 29 28 27 26 25 Pullup/Pulldown nCLK1 CLK2 1 CLK9 24 Pulldown CLK2 nCLK2 2 23 nCLK9 Pullup/Pulldown nCLK2 VCC 3 22 SEL0 Q Q 4 21 SEL1 nQ SEL2 nQ 5 20 VEE 6 19 SEL3 7 CLK8 CLK3 18 8 nCLK8 nCLK3 17 9 10 11 12 13 14 15 16 Pulldown CLK11 Pullup/Pulldown nCLK11 ICS853S012I SEL 3:0 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View 2017 Integrated Device Technology, Inc. 1 August 23, 2017 nCLK4 nCLK1 CLK4 CLK1 nCLK5 nCLK0 CLK5 CLK0 CLK6 CLK11 nCLK6 nCLK11 CLK10 CLK7 nCLK7 nCLK10ICS853S012I Datasheet Table 1. Pin Descriptions Number Name Type Description 1 CLK2 Input Pulldown Non-inverting differential clock input. Pullup/ 2 nCLK2 Input Inverting differential clock input. V /2 default when left floating. CC Pulldown 3V Power Positive supply pin. CC 4, 5 Output Differential output pair. LVPECL interface levels. Q, nQ 6V Power Negative supply pin. EE 7 CLK3 Input Pulldown Non-inverting differential clock input. Pullup/ 8 nCLK3 Input Inverting differential clock input. V /2 default when left floating. CC Pulldown Pullup/ 9 nCLK4 Input Inverting differential clock input. V /2 default when left floating. CC Pulldown 10 CLK4 Input Pulldown Inverting differential clock input. Pullup/ 11 nCLK5 Input Inverting differential clock input. V /2 default when left floating. CC Pulldown 12 CLK5 Input Pulldown Inverting differential clock input. 13 CLK6 Input Pulldown Non-inverting differential clock input. Pullup/ 14 nCLK6 Input Inverting differential clock input. V /2 default when left floating. CC Pulldown 15 CLK7 Input Pulldown Non-inverting differential clock input. Pullup/ 16 nCLK7 Input Inverting differential clock input. V /2 default when left floating. CC Pulldown Pullup/ 17 nCLK8 Input Inverting differential clock input. V /2 default when left floating. CC Pulldown 18 CLK8 Input Pulldown Inverting differential clock input. 19, 20, SEL3, SEL2, Input Pulldown Clock select input pins. LVCMOS/LVTTL interface levels. 21, 22 SEL1, SEL0 Pullup/ 23 nCLK9 Input Inverting differential clock input. V /2 default when left floating. CC Pulldown 24 CLK9 Input Pulldown Inverting differential clock input. Pullup/ 25 nCLK10 Input Inverting differential clock input. V /2 default when left floating. CC Pulldown 26 CLK10 Input Pulldown Inverting differential clock input. Pullup/ 27 nCLK11 Input Inverting differential clock input. V /2 default when left floating. CC Pulldown 28 CLK11 Input Pulldown Inverting differential clock input. 29 CLK0 Input Pulldown Inverting differential clock input. Pullup/ 30 nCLK0 Input Inverting differential clock input. V /2 default when left floating. CC Pulldown 31 CLK1 Input Pulldown Inverting differential clock input. Pullup/ 32 nCLK1 Input Inverting differential clock input. V /2 default when left floating. CC Pulldown NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 2017 Integrated Device Technology, Inc. 2 August 23, 2017