Low Skew, 1-to-4 8523I-03 Differential-to-LVHSTL Fanout Buffer DATA SHEET GENERAL DESCRIPTION FEATURES The 8523I-03 is a low skew, high performance 1-to-4 Dif- 4 differential LVHSTL compatible outputs ferential-to-LVHSTL fanout buffer. The 8523I-03 has two Selectable differential CLK0, nCLK0 and CLK1, nCLK1 selectable clock inputs.The input pairs can accept most clock inputs standard differential input levels. The clock enable is internally synchronized toeliminate runt pulses on the Clock input pairs can accept the following differential outputs during asynchronousassertion/deassertion of the clock input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL enable pin. Maximum output frequency: 650MHz Guaranteed output and part-to-part skew character- Translates any single-ended input signal to LVHSTL istics make the 8523I-03 ideal for those applications levels with resistor bias on nCLK input demanding well de ned performance and repeatability. Output skew: 50ps (maximum) Part-to-part skew: 400ps (maximum) Propagation delay: 1.2ns (typical) V = 1V (maximum) OH 3.3V core, 1.8V output operating supply Lead-Free package available -40C to 85C ambient operating temperature BLOCK DIAGRAM PIN ASSIGNMENT 1 20 Q0 GND 2 19 nQ0 CLK EN 3 18 VDDO CLK SEL 4 17 CLK0 Q1 5 16 nQ1 nCLK0 6 15 Q2 CLK1 7 14 nQ2 nCLK1 8 13 VDDO nc 9 12 nc Q3 10 11 nQ3 VDD 8523I-03 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm body package G Package Top View 8523I-03 REVISION A 11/9/15 1 2015 Integrated Device Technology, Inc.8523I-03 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 GND Power Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follow clock 2 CLK EN Input Pullup input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects differential CLK1, nCLK1 inputs. 3 CLK SEL Input Pulldown When LOW, selects CLK0, nCLK0 inputs. LVCMOS / LVTTL interface levels. 4 CLK0 Input Pulldown Non-inverting differential clock input. 5 nCLK0 Input Pullup Inverting differential clock input. 6 CLK1 Input Pulldown Non-inverting differential clock input. 7 nCLK1 Input Pullup Inverting differential clock input. 8, 9 nc Unused No connect. 10 V Power Core supply pin. DD 11, 12 nQ3, Q3 Output Differential output pair. LVHSTL interface levels. 13, 18 V Power Output supply pins. DDO 14, 15 nQ2, Q2 Output Differential output pair. LVHSTL interface levels. 16, 17 nQ1, Q1 Output Differential output pair. LVHSTL interface levels. 19, 20 nQ0, Q0 Output Differential output pair. LVHSTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN R Input Pullup Resistor 51 K PULLUP R Input Pulldown Resistor 51 K PULLDOWN LOW SKEW, 1-TO-4 2 REVISION A 11/9/15 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER